Technical Program

Thursday, June 03, 2010

Session 14: 2nd-Level Interconnect
8:00 a.m. - 11:40 a.m.
Committee: Interconnections
Versailles 1 & 2

Session Co-Chairs:

Senol Pekin
Intel Corporation
T +1-480-552-4898
F +1-480-552-1304
spekin@msn.com

Flynn Carson
STATS ChipPAC, Inc.
T +1 510-979-8338
F +1 510-979-8009
flynn.carson@statschippac.com

Papers:

1. 8:00 AM - Effects of Thermal Cycling Parameters on Lifetimes and Failure Mechanism of Solder Interconnections
T.T. Mattila- Aalto University
H. Xu- Aalto University
O. Ratia- Aalto University
M. Paulasto-Kröckel- Aalto University

2. 8:25 AM - High Resolution Analysis of Intermetallic Compounds in Microelectronic Interconnects Using Electron Backscatter Diffraction and Transmission Electron Microscopy
M. Krause- Fraunhofer IWM
B. März- Fraunhofer IWM
S. Bennemann- Fraunhofer IWM
M. Petzold- Fraunhofer IWM

3. 8:50 AM - Solder Joint Reliability Performance of Electroplated SnAg Mini-Bumps for WLCSP Applications
Luke England- Fairchild Semiconductor

4. 10:00 AM - Layer Misregistration in PCB and Its Effects on Signal Propagation
Lei Shan- IBM Corporation
Young Kwark- IBM Corporation
Christian Baks- IBM Corporation
Mark Ritter- IBM Corporation
Boping Wu- University of Washington

5. 10:25 AM - Advanced Trench Filling Process by Selective Copper Electrodeposition for Ultra Fine Printed Wiring Board Fabrication
Hiroshi Nakano- Hitachi, Ltd.
Hitoshi Suzuki- Hitachi, Ltd.
Toshio Haba- Hitachi, Ltd.
Hiroshi Yoshida- Hitachi, Ltd.
Akira Chinda- Hitachi Cable Ltd.
Haruo Akahoshi- Hitachi, Ltd.

6. 10:50 AM - Investigation for Electromigration-Induced Hillock in a Wafer Level Interconnect Device
Yuan Xiang Zhang- Zhejiang University of Technology
Lihua Liang- Zhejiang University of Technology
Yong Liu- Fairchild Semiconductor Corporation

7. 11:15 AM - 3D Mobile CPU System Assembly by Z-Axis Stack Connector Solutions
Omer Vikinski- Intel Corporation
Rami Ben-Ezra- Intel Corporation