Technical Program
Friday, June 04, 2010
Session 36: Chip Package Interaction: Low-k, ULK, BGA
1:30 PM - 5:10 PM
Committee: Assembly & Manufacturing Technology
Champagne 4
Session Co-Chairs:
|
Mali Mahalingam Freescale Semiconductor, Inc. T +1-480-413-5368 F +1-480-413-4385 mali.mahalingam@freescale.com |
Sharad Bhatt Shanta Systems, Inc. T +1-814-362-6996 F +1-814-362-9922 sharad_bhatt@ieee.org |
Papers:
1. 1:30 PM - Pb-Free Solder Joint Reliability of Fine Pitch Chip-Scale Packages
Weidong Xie- Cisco Systems, Inc.
Tae-Kyu Lee- Cisco Systems, Inc.
Kuo-Chuan Liu- Cisco Systems, Inc.
Jie Xue- Cisco Systems, Inc.
2. 1:55 PM - The Interaction between Grain Orientation Evolution and Thermal Cycling as a Function of Position in Ball Grid Arrays Using Orientation Image Microscopy
Tae-Kyu Lee- Cisco Systems, Inc
Bite Zhou- Michigan State University
Lauren Blair- Michigan State University
Kuo-Chuan Liu- Cisco Systems, Inc
Jie Xue- Cisco Systems, Inc
Thomas R. Bieler- Michigan State University
3. 2:20 PM - Neural Network Modeling to Predict Quality and Reliability for BGA Solder Joints
Sebastian Meyer- Technische Universität Dresden
Heinz Wohlrabe- Technische Universität Dresden
Klaus-Jürgen Wolter- Technische Universität Dresden
4. 3:30 PM - Solutions for 45/50nm ELK Device Integration into Flip Chip and Wire Bond Packaging
John Beleran- United Test And Assembly Center, Ltd.
Hua Hong Tan- United Test And Assembly Center, Ltd.
P.L. Wilson Ong- United Test And Assembly Center, Ltd.
X.R. Zhang- United Test And Assembly Center, Ltd.
Gatbonton Librado Amurao- United Test And Assembly Center, Ltd.
Gaurav Mehta- United Test And Assembly Center, Ltd.
W.H. Zhu- United Test And Assembly Center, Ltd.
5. 3:55 PM - Chip Package Interaction (CPI) Reliability of Low-k/ULK Interconnect with Lead Free Technology
Lei Fu- Advanced Micro Devices
Michael Su- Advanced Micro Devices
Ashok Anand- Advanced Micro Devices
Edwin Goh- Advanced Micro Devices
Frank Kuechenmeister- Globalfoundries
6. 4:20 PM - A Challenge of 45 nm Extreme Low-k Chip Using Cu Pillar Bump as 1st Interconnection
Po-Jen Cheng- Advanced Semiconductor Engineering, Inc.
C.M. Chung- Advanced Semiconductor Engineering, Inc.
T.M. Pai- Advanced Semiconductor Engineering, Inc.
D.Y. Chen- Advanced Semiconductor Engineering, Inc.
7. 4:45 PM - Below 45nm Low-k Layer Stress Minimization Guide for High-Performance Flip-Chip Packages with Copper Pillar Bumping
EunSook Sohn- Amkor Technology, Korea
Jin Young Kim- Amkor Technology, Korea
Jae Dong Kim- Amkor Technology, Korea
Choon Heung Lee- Amkor Technology, Korea