Professional Development Courses

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1. Achieving High Reliability of Lead-Free Soldering -Materials Consideration
Course Leader(s) Ning-Cheng Lee Indium Corporation

Course Objective: This course covers the detailed material considerations required for achieving high reliability for lead-free solder joints. The reliability discussed includes joint mechanical properties, development of type and extent of intermetallic compounds (IMC) under a variety of material combinations and aging conditions and how those IMCs affect the reliability. The failure modes, thermal cycling reliability, and fragility of solder joints as a function of material combination, thermal history, and stress history will be addressed in details, and novel alloys with reduced fragility will be presented. Electromigration, corrosion, and tin whisker will also be discussed. Furthermore, the reliability of through-hole solder joints will be reviewed, and recommendation will be provided, particularly for thick boards. The emphasis of this course is placed on the understanding of how the various factors contributing to the failure modes, and how to select proper solder alloys and surface finishes for achieving high reliability. Also will be presented are the desirable future alloys and fluxes in order to meet the challenge of miniaturization.

Course Outline:
• Implementation Status
• Prevailing Materials - Alloys and Finishes
• Surface Finishes Issues - ENIG, ImAg, and ImSn
• Mechanical Properties - Shear, Pull, and Creep
• Intermetallic Compounds - Effect of Cu, Ni, Other Additives, and Heat History
• Failure Modes - Grain Deterioration, Orientation, Mixed Alloys, and Interfacial Voiding
• Thermal Cycle Reliability - Effect of Cycling Condition, Surface Finishes, and Reflow Temperature
• Reliability of Through-Hole Joints - Large and Thick Boards, Partially Filled Through-hole
• Fragility - Effect of Surface Finishes, Alloys, Reflow, Strain Rate, Aging, Cycling, and IMC
• Electromigration - Effect of Current Density, Back Stress, and Cu UBM Thickness
• Corrosion - SAC and Performance of Surface Finishes Under Harsh Conditions
• Tin Whisker - Causes of Formation, Methods for Control

Who Should Attend: Any one who care about achieving high reliability lead-free solder joints and like to know how to achieve it should take this course.

Author Bio(s): Ning-Cheng Lee is the Vice President of Technology of Indium Corporation. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 20 years of experience in the development of fluxes and solder materials for SMT industries. He received his PhD in polymer science from University of Akron in 1981, and a BS in chemistry from National Taiwan University in 1973. Ning-Cheng is the author of “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies”, and co-author of “Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials”. He received 1991 award from SMT Magazine and 1993 and 2001 awards from SMTA for best proceedings papers of SMI and SMTA international conferences, and 2008 award from IPC for Honorable Mention Paper – USA Award of APEX conference. He was honored as 2002 SMTA Member of Distinction, and received 2003 Lead Free Co-Operation Award from Soldertec, and received 2006 Exceptional Technical Achievement Award from CPMT. He serves on the SMTA board of directors.

2. UltraHigh-Thermal-Conductivity Packaging Materials
Course Leader(s) Carl Zweben Thermal Materials Consultant

Course Objective: This course provides an in-depth discussion of the increasing number of ultrahigh-thermal-conductivity materials that address key packaging problems: heat dissipation, warpage and fracture of low-k dielectric layers, solder joints, etc., arising from differences in coefficient of thermal expansion (CTE). Topics include properties, manufacturing processes, applications, cost, lessons learned, and future directions, including carbon nanotubes. Traditional materials are also covered. There are now many low-CTE, low-density materials with thermal conductivities as high as 1700 W/m-K, over four times that of copper (400 W/m-K). Thermally-conductive carbon fibers allow heat removal through printed circuit boards, and can tailor CTE, potentially eliminating the need for underfill. Carbon nanotubes and other high-performance graphitic materials can greatly increase thermal interface material (TIM) thermal conductivity. Low-CTE solders under development will provide additional advantages. Advanced materials are being used in an increasing number of commercial and aerospace microelectronic and optoelectronic applications, including servers, laptops, phased array antennas, telecommunication equipment, laser diodes, LED solid state lighting, plasma and liquid crystal displays, photovoltaics, sensors, instruments, etc. For example, low-CTE diamond particle-reinforced SiC heat spreaders having a thermal conductivity of over 600 W/m-K were used in IBM servers.

Course Outline:
• Key heat dissipation, thermal stress and warping problems
• What is wrong with traditional materials? Overview of their properties
• Classes of ultrahigh thermal conductivity materials: monolithic and composite
• Properties of key monolithic carbonaceous materials
• Properties of key metal matrix composites
• Properties of key ceramic matrix composites
• Properties of key carbon matrix composites
• Properties of key polymer matrix composites
• Thermally conductive, low-CTE printed circuit boards
• High-performance thermal interface materials
• Manufacturing methods for advanced materials
• Using advanced materials to improve manufacturing yield
• Lessons learned
• Cost considerations
• Applications of ultrahigh-thermal-conductivity-materials
• Future directions, including carbon nanotubes and nanofibers, graphite nanoplatelets, etc.

Who Should Attend: Engineers, scientists and managers involved in microelectronic, optoelectronic and MEMS/MOEMS thermal management and packaging design, production and R&D; material suppliers.

Author Bio(s): Dr. Zweben, now an independent consultant, has directed development and application of advanced electronic packaging and thermal management materials for over 35 years. He was the first to use silicon carbide particle-reinforced aluminum (Al/SiC) and other advanced thermal materials in electronic packaging. He was formerly Advanced Technology Manager and Division Fellow at GE Astro Space. Other affiliations have included Du Pont, Jet Propulsion Laboratory, Materials Sciences Corporation, and the Georgia Tech NSF Packaging Research Center. Dr. Zweben was the first, and one of only two winners of both the GE One-in-a-Thousand and Engineer-of-the-Year awards. He is a Life Fellow of ASME, a Fellow of ASM and SAMPE, an Associate Fellow of AIAA. He was a Distinguished Lecturer for AIAA and ASME. He has published and lectured widely on advanced thermal materials, and is Co-Editor-in-Chief of the six-volume Comprehensive Composite Materials. Dr. Zweben has directed and lectured at over 200 short courses for many organizations, including ECTC, SemiTherm, ASME, Nokia, Delphi Electronics, Coherent Laser, Rogers Corporation, BAE Systems, Boeing, Lockheed Martin, Northrop Grumman, ITT, Reynolds, Princeton University High Energy Physics Group, the Electro-Optics Center, the US Air Force, and others. He received the UCLA Certificate of Appreciation for Excellence in Teaching.

3. Wafer Level-Chip Scale Packaging
Course Leader(s) Luu Nguyen National Semiconductor

Course Objective: Wafer Level-Chip Scale Packaging (WL-CSP) has gained momentum in the small chip arena, driven by needs for cost reduction, form factor shrinkage, and enhanced performance. This course will provide an overview of the WL-CSP technology. The market drivers, benefits, and challenges facing industry-wide adoption will be discussed. The current WL-CSP configurations will be reviewed in terms of their construction, manufacturing process, and published electrical and thermal performance, together with package and board level reliability. Since the technology marks the convergence of fab, assembly, and test, discussion will also address some fundamental issues such as: 1. Does it fit best with front-end or back-end processing? 2. Will it be applicable and cost-effective for memory and other complex devices such as ASICs and microprocessors? 3. Are the current standards for design rules, outline, and reliability applicable? Extensions to higher pin count packages and other arenas such as RF and MEMS will be reviewed.

Course Outline:
• 1. Wafer Level-Chip Scale Packaging (WL-CSP) definition
• 2. Market drivers for WL-CSPs
• 3. Benefits of WL-CSPs
• 4. Barriers and challenges for WL-CSPs
• 5. Review of current WL-CSPs in the industry (Bump on Pad, Bump on Polymer, Fan-out configurations)
• 6. Wafer level testing – status and challenges
• 7. Infrastructure service providers
• 8. Case studies of WL-CSPs (structures, processing, reliability, applications)
• 9. Extension of WL-CSP concept to other arenas (sensors, imaging, MEMS, etc.)
• 10. Future trends: enhanced lead-free solder balls, large die size, wafer level underfill, thin and ultra thin WL-CSP, RDL (redistribution layer), stacked WL-CSP, MCM in “reconstituted wafers,” embedded components, etc.)

Who Should Attend: The course will be useful to the following three groups of engineers and scientists: 1. Newcomers to the field who would like to obtain a general overview of WL-CSP. 2. R&D practitioners who would like to learn new methods for solving CSP problems. 3. Those considering WL-CSP as an alternative for their interconnect systems.

Author Bio(s): L. T. Nguyen is a Senior Engineering Manager in the Packaging Research Group at National Semiconductor Corp., working on various aspects of wafer-level packaging, lead-free and halogen-free, thermal measurement and modeling, design-for-manufacturability, design-for-reliability, precision analog, printed electronics, and MEMS. He received his Ph.D in Mechanical Engineering from MIT, and has worked at IBM Research and Philips Research. He co-edited two books on packaging, and has close to 200 publications. He has over 70 patents and invention disclosures. He is a Fellow of IEEE and ASME, and a Fulbright Scholar (Finland 2002). He is currently an Associate Editor for the IEEE Transactions on Advanced Packaging, IEEE Transactions on Components and Packaging Technologies, and IEEE Transactions on Electronics Packaging Manufacturing. He was a Guest Editor for the T-EPM for a special issue on Drop Testing, and the T-ADvP for two issues on Wafer Level Packaging. He received two Best of Conference Awards (27th IEMT 2002 and InterPack 2005) and eight IMAPS and IEMT Best of Session Conference Awards. Other awards include the 2003 Mahboob Khan Outstanding Mentor Award from the Semiconductor Research Corporation in recognition of contributions to student mentoring, research collaboration, and technology transfer, and the 2004 IEEE CPMT Outstanding Sustained Technical Contributions Award. He has also been involved with an Engineering Council since 2002 to develop a comprehensive program to foster professional development, practical training, best practices sharing, mentoring, cross-training, and e-learning among more than 2,500 National Semiconductor engineers worldwide. These efforts were recognized with the IEEE Educational Activities Board Employer Professional Development Award (2005), the IEEE Region 6 Outstanding Corporate Engineering Community Service Award (2006), and the European Electronics Industry Elektra “Investing in People” Award (2006).

4. 3D IC Integration
Course Leader(s) Philip Garrou Microelectronic Consultants of NC

Course Objective: This course is based on the authors activity over the past 6 years with numerous companies in the industry, his weekly 3D blog “Perspectives From the Leading Edge “ in Semiconductor International and the 2 volume Wiley-VCH book “Handbook of 3D IC Integration: Technology and Applications of 3D IC Circuits” which the author authored and edited. The course will begin by defining and contrasting 3D Integration (thinning, bonding and TSV) to 3D packaging (thinning stacking and wire bonding to the BGA base) . The various drivers for 3D integration including the electrical performance and economic issues will be examined. We will examine the various process sequences being proposed for 3D integration and the process unit operations necessary to fabricate a 3D stack. The processes sequences proposed by IDMs, Universities, and Institutes will be compared and contrasted. We will then examine the applications expected to be the early and later adopters for 3D technology and the evolving infrastructure that will be necessary to accomplish this. The course will end by looking the remaining technical and market barriers ( design, thermal and test) and looking at the current best sources of 3D information.

Course Outline:
• 3D Packaging
• 3D IC Integration
• 3D definitions
• 3D process sequences
• 3D Processing
• Processes at Univ, Institutes, IDMs
• Applications - CIS, memory, memory on logic etc
• Infrastruture development - design, foundries, OSATS
• remaining barriers
• conslusions

Who Should Attend: The course will be aimed at technical personnel wanting a status review of the subject and marketing/management personnel looking for a status report to help determine their position in the business food chain.

Author Bio(s): Dr. Garrou currently consults in the areas of thin film technology, IC packaging, microelectronic materials and 3D IC integration. From 2002 – 2004 he was Director of Technology for Dow Chemicals Advanced Electronic Materials business. From 1997 – 2002 he was General Manager of Dows BCB dielectric business. Dr. Garrou is a fellow of IEEE & IMAPS and has served as President of the IEEE CPMT (2003-2005) and IMAPS (1998). Dr. Garrou has been Associate Editor of IEEE Transactions on Components and Packaging. He is currently a contributing editor and 3D IC blogger for Semiconductor International. He has authored > 100 technical publications. He edited and authored the McGraw Hill Multichip Module Handbook (1998) and Wiley-VCH Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits (2008). Awards: 2000 - IMAPS Ashman award for “…technical achievement in Microelectronics Packaging”. 2002 - Fraunhofer IZM International Adv Packaging Award for “..pioneering achievement in the introduction of new thin film polymeric packaging materials.” 2007 - IEEE CPMT Sustained Technical Achievement Award for “..for 25 years of technical contributions and leadership in thin film dielectric materials and microelectronic applications including multichip modules, bumping and wafer level packaging, integrated passives and 3D integration”

5. Nanopackaging Applications and Modeling
Course Leader(s) Chris Bailey University of Greenwich James James Portland State University

Course Objective: This course will detail the state-of-the-art in nanopackaging technologies, and associated modeling techniques, related to thermal management, electrical performance, and reliability improvement of Microsystems devices. The prevalent nanotechnologies being applied are nanoparticles and carbon nanotubes (CNTs), but there are also examples of nanowires and shrinkage of physical dimensions. Nano properties which are being exploited include, melting point depression, sintering, the Coulomb blockade, theoretical maximum mechanical strengths in single grain material structures, enhanced chemical activities, and unique optical scattering properties. The first half of the course will begin with an introduction to Microsystems packaging for context, and will then focus on how nano materials and technologies are being applied to enhance packaging performance and overall reliability. The packaging needs for future generations of nanoelectronic devices will also be discussed. The second half of the course will discuss the latest advances in multi-physics/scale modeling technologies that predict the impact of nanotechnologies on the functional and structural performance of the package. This will include details on current state of the art in multi-scale modeling techniques (i.e. Finite Element Analysis to Molecular Dynamics), physics-of-failure models and a discussion on the future challenges that modeling techniques will need to address.

Course Outline:
• Introduction to Nanotechnologies in Microsystems Packaging
• Nanoparticle and carbon nanotube fabrication
• Nanoparticle properties: melting point depression, coulomb block, sintering, optical, etc
• Nanoparticles in Solders, Conductive Adhesives, underfills, microvias, conductive inks, etc.
• Carbon Nanotube characterization (chirality, etc), and properties
• Carbon Nanotubes for thermal management, electromagnetic shielding, and interconnect reliability
• Packaging requirements for future CMOS and Post-CMOS nanoelectronics
• Molecular dynamics and Finite Element simulations of packaging
• Multi-Physics/Scale Models and Modelling across the length scales
• Modelling Fabrication of Nano-Structures
• Nanopackaging Modelling: Application for Thermal, Electrical and Mechanical behavior
• Impact of Nanotechnology on Physics-of-Failure Reliability Modelling
• Details on current modelling software tools.
• Future Requirements and Trends in Nanopackaging Modelling Tools

Who Should Attend: The course will be beneficial to electrical, mechanical, and materials engineers alike, or anyone with an interest in microsystem device design, fabrication, assembly, or application. The level will be introductory, and accessible to students and graduates in any of these areas or the physical sciences.

Author Bio(s): Chris is Professor of Computational Mechanics and Reliability at the University of Greenwich, London, United Kingdom. He received his PhD in Computational Modeling in 1988, and an MBA in Technology Management in 1996. He has published over 200 papers on Design and Simulation of micro/nano-technology based processes and products and has managed many UK and International projects and worked closely with over 100 companies with regards thier design, simulation and modelling requirements. Chris is a member of the NAFEMS Multi-Physics/Scale Modelling working group, a senior member of IEEE-CPMT, and a UK Committee member of IMAPS. In 2003 he was the Royal Society visiting Professor to Hong Kong. In 2007 he was and Programme Chair for High Density Packaging Conference in Shanghai, China, and also the local organizer of the IEEE sponsored EuroSime conference in London. In 2008 he was the General Chair for the Electronics System-integration Technology Conference (ESTC-2008) in Greenwich, London.

James E. Morris is a Professor of Electrical & Computer Engineering at Portland State University, Oregon, and an IEEE Fellow. Professor Morris is an IEEE-CPMT Distinguished Lecturer, and won the 2005 CPMT David Feldman Outstanding Contribution Award. He is an Associate-Editor of the IEEE Transactions on Components & Packaging Technology, and has edited four books on electronics packaging, with “Nanopackaging: Nanotechnologies and Electronics Packaging” from Springer the most recent. Recently appointed as the CPMT Society representative on the IEEE Nanotechnology Council, he has establishd a NTC Nanopackaging technical committee to act as a Nanopackaging program committee for the annual IEEE NANO conference, and has instituted a regular Nanopackaging column in the IEEE Nanotechnology magazine. His research activities have been focused recently on electrically conductive adhesives and the electrical conduction mechanisms in discontinuous thin metal films, with applications to nanopackaging and single-electron transistor nanoelectronics, but with continuing projects in device modeling and sensors too. Over the past year, he has held the Nokia-Fulbright Fellowship at Helsinki University of Technology, following an Erskine Fellowship at the University of Canterbury, N.Z., and research appointments at the University of Greenwich, Dresden University of Technology, and Chalmers University of Technology.

6. Moisture Related Reliability in Electronic Packaging
Course Leader(s) Xuejun Fan Lamar University

Course Objective: Course Scope: This course will present a state-of-art and in-depth overview of recent advances in moisture related reliability studies in IC packaging. The course provides fundamental knowledge and understanding on the failure mechanisms associated with moisture, such as delamination/cracking during reflow, material and interface degradation during HAST, and the electrochemical metal migration under biased HAST condition. The course will cover the fundamental understandings in moisture diffusion, anomalous moisture diffusion behaviors, water sorption versus moisture sorption, and moisture states in polymers. The characterization of moisture related properties, such as diffusivity, solubility, saturated moisture concentration, and the hygroscopic swelling, and adhesion will be discussed. Vapor pressure evolution at reflow, especially for lead-free applications, will be described. The accelerated moisture sensitivity/reflow test will be introduced, with a focus on the acceleration methodology development. The impact of hygroscopic swelling on copper/low K structures as well as under bump metallurgy (UBM) failures will be presented. The effect of moisture on material properties, especially on adhesion degradation, will be described. Two types of electrochemical metal migration under biased HAST condition are explained. Several case studies concerning mold compound, underfill, and die-attach moisture performance will be presented. Course Objectives: 1)Fundamental understanding of moisture diffusion and moisture states in polymers; 2) Material characterization and techniques of moisture related properties; 3)Accelerated moisture sensitivity/reflow test methodology; 4)Effect of moisture on material properties; 5)Principles of electrochemical metal migration; and 6)Case studies

Course Outline:
• Introduction
• Moisture related reliability test and specifications – MSL, HAST, BHAST etc
• Typical failure modes and failure mechanisms due to moisture
• Moisture diffusion, anomalous moisture diffusion, moisture sorption vs. water sorption, moisture diffusion finite element modeling
• Characterization of moisture related material properties
• Vapor pressure evolution at reflow temperature
• Hygroscopic swelling
• Effect of moisture on material properties
• Accelerated moisture sensitivity/reflow test
• Electrochemical metal migration due to moisture
• Case studies – mold compound, underfill and die-attach performance in various packages

Who Should Attend: The course is designed for staff members, technical managers, design and manufacturing personnel, and reliability engineers in microelectronic companies. Although the course reviews most recent advances in moisture related reliability issues, the course does not assume prior knowledge of these issues and hence is of interest for both experts and new actors in this area.

Author Bio(s): Chandler, Arizona, from 2004 to 2007, a Senior Member Research Staff with Philips Research Lab at Briarcliff Manor, New York from 2001 to 2004, and a Member Technical Staff and Group Leader at the Institute of Microelectronics (IME), Singapore from 1997 to 2000. Dr. Fan has been active in instructing short courses in the area of reliability mechanics of IC packaging and microsystems. In 2008, he is elected as CPMT Distinguished Lecturer. In 2009 he received 2008 the 2008 Best Paper Award of IEEE Transactions on Components and Packaging Technologies. Dr. Fan’s interests and expertise lie in the areas of design, modeling, material characterization, and reliability in micro-/nano- electronic packaging and microsystems. He has published more than 100 scientific papers and filed 5 patents in world-wide patent offices. In his earlier career as a university faculty in China from 1989 to 1997, he received the Young Scientist Fellowship from Japan Society of Promotion of Science to spend a year at the University of Tokyo in 1993. He was a visiting professor at the University of British Columbia, Vancouver, Canada from 1996 to 1997. Dr. Fan was promoted to a full professor at Taiyuan University of Technology, Taiyuan, Shanxi in 1991, and became one of the youngest professors in China when he was 27. He was a nominee for the title of “1991 Ten Outstanding Youth of China”, and received Young Faculty Award in 1994 from Fok Ying-Tung Education Foundation.

7. Fundamentals and Applications of Package Reliability Predictions
Course Leader(s) Shubhada Sahasrabudhe Intel Corporation

Course Objective: Abstract: The objective of the course is to provide an overview of Knowledge Based Risk Assessment methodology that uses the knowledge of field environment to develop a quality and reliability requirement plan. • The key to the success of this methodology is appropriate definition of the Use Conditions (UC). The course will discuss different techniques for collecting UC data and will highlight specific examples related to air temperature/humidity definition using NOAA weather data. • Considerations to extreme UC will be discussed. • The course will further outline different reliability tests and their correlation to UC. • Typical package failure mechanisms (FM) will be discussed along with key Failure Analysis techniques. • The course will then highlight reliability data analysis concepts like bath tub curve (extrinsic/intrinsic FM), life distribution fitting (Lognormal/Weibull/Exponential for interval and right censored data), accelerated life modeling (single and multi parameter using life regression analysis techniques) and field life prediction. • A methodology for defining reliability requirements and test plans to envelope different FM, market segments and reliability tests will be outlined along with discussion on sample sizes and confidence levels. • In class reliability statistics exercises will help students practice skills. • Target Audience: Engineers working on Packaging, Reliability, Materials

Course Outline:
• Introduction to UC. Definitions of Quality and Reliability
• Reliability tests and their correlation to Use Conditions
• Typical Package fail mechanisms
• Key Failure Analysis Techniques
• Statistical analysis methods
• Reliability requirement definitions
• In class exercises

Who Should Attend: Target Audience: Engineers working on Packaging, Reliability, Materials

Author Bio(s):

8. Packaging of High Brightness LED for Solid State Lighting
Course Leader(s) Ricky Lee HKUST Sheng Liu Huazhong University of Science and Technology

Course Objective: Light emitting diode (LED) is a semiconductor device based on the effect of electroluminescence. Due to the limitation in efficacy and the lack of white light, LED was not suitable for general lighting applications in the past. With the advancement of semiconductor materials and packaging technologies, the illumination performance of LED has been greatly improved. Ten years ago high power (one watt) white LEDs were introduced with efficiencies high enough to kick off serious discussion on using LEDs for solid state lighting (SSL) applications. Over the last decade the performance of high brightness LED (HB-LED) has continued to increase from about 20 Lumens/Watt to over 100 Lumens/Watt today. There is no longer any doubt about the feasibility of LEDs for SSL. The remaining question is when LEDs will dominate all lighting markets. SSL has major advantages such as energy saving, environmental friendliness, and long operational life. LED Packaging is the major enabling technology to achieve these merits. This short course will review the technology trends of lighting sources and introduce the features of LED. Technical issues in packaging LED components such as interconnection, phosphor deposition, and encapsulation will be elaborated in detail. Considerations in thermal and power management will be evaluated. Efforts will also be made to investigate optical design, analysis and characterization. Applications of HB-LED for general SSL and special lighting will be highlighted. Furthermore, technology roadmap and IP issues will be discussed.

Course Outline:
• Review of electroluminescence and lighting technology trends
• Overview of packaging structures of LED Interconnection and verticle LED
• Phosphor deposition for color tuning
• Encapsulation materials and processes Considerations in thermal Management
• Optical design, analysis and characterization
• HB-LED arrays for general solid state lighting
• HB-LED modules for special lighting applications
• Driving circuit and intelligent control design
• Reliability engineering of HB-LED packaging
• LED measurement and standards
• Technology roadmap and patent mapping

Who Should Attend: This short course is intended for scientists in research institutions, faculty members and postgraduate students in universities, professional engineers and technical managers in the industries who are involved or interested in the design, materials, processing, and assembly of high brightness LED for solid state lighting.

Author Bio(s): Ricky Lee received his PhD degree from Purdue University. Currently he is Professor of Mechanical Engineering and Director of Center for Advanced Microsystems Packaging (CAMP) at the Hong Kong University of Science & Technology (HKUST). His research activities cover flip chip technologies and wafer level packaging, through silicon vias and 3D packaging, LED and optoelectronics packaging, lead-free soldering and solder joint reliability. Ricky has substantial publications in international journals/conference proceedings and received several best paper awards. He also co-authored three books and owns three technical patents. Ricky is Fellow of IEEE and ASME, and Institute of Physics (UK). In addition, he is elected IEEE CPMT Distinguished Lecturer and receives CPMT Electronics Manufacturing Technology Award. Furthermore, he serves as Editor-in-Chief of IEEE Transactions on Components & Packaging Technologies and Associate Editor of IEEE Transactions on Advanced Packaging. Ricky is the project leader to implement HB-LED SSL on Hong Kong subway trains.

Sheng Liu is a Changjiang scholar professor of Mechanical Engineering at Huazhong University of Science and Technology and he has a dual appointment at Wuhan National Laboratory for Optoelectronics. He once was a tenured faculty at Wayne State University. He has over 17 years experience in LED/MEMS/IC packaging. He has extensive experience in consulting with many leading multinational and Chinese companies. He once won prestigious White House/NSF Presidential Faculty Fellow Award in 1995, ASME Young Engineer Award in 1996, NSFC Overseas Young Scientist Award in 1999 in China, IEEE CPMT Exceptional Technical Achievement Award in 2009, and Chinese Electronic Manufacturing and Packaging Technology Society Special Achievement Award in 2009. He has been an associate editor of IEEE Transaction on Electronic Packaging Manufacturing since 1999 and an associate editor of Journal of Frontiers of Optoelectronics in China since 2007. He is currently one of 11 National Committee Members in LED under Ministry of Science and Technology of China from 2006-2011. He obtained his Ph.D. from Stanford University in 1992. He is ASME Fellow. He has filed and owed more than 80 patents in China and USA, and has published more than 300 technical articles, edited more than 9 proceedings in English for ASME and IEEE, he has co-authored the first book in LED packaging for lighting applications, which will appear at the end of 2009.

9. Finite Element Simulation and Life Prediction for Solder Joint Reliability
Course Leader(s) Ahmer Syed Amkor Technology

Course Objective: The primary objective of this course is to prepare participants to conduct solder joint reliability simulation and prediction. A summary of thermal and mechanical loading conditions acting on electronic assemblies will first be presented with associated damage mechanisms. Constitutive equations governing the response of both SnPb and Pb free solder will be summarized. This will be followed with detailed discussion on advanced finite element modeling and solution techniques and their application for solder joint reliability prediction. The participants will be able to develop skill to understand the damage mechanisms and apply simulation techniques that have been proven to be effective, efficient, and highly accurate. This will cover modeling and solution techniques for temperature cycle, drop/shock, cyclic bending, and vibration loading conditions. The course will focus on technical and practical aspects of finite element modeling for electronic assemblies.

Course Outline:
• Introduction to thermal and mechanical loading conditions
• Damage mechanisms and failure statistics
• SnPb and SAC solder constitutive equations and material modeling
• Modeling assumptions and their impact on response of critical solder joints
• Simulation techniques for thermal cycle reliability
• PWB, component, and joint level simulation for board level drop and cyclic bend
• Life prediction Models for SnPb and SAC solder

Who Should Attend: This course is intended for practitioners of finite element simulations for electronic assemblies, reliability engineers, package and system level product engineers, and managers who plan to implement virtual reliability predictions in their companies.

Author Bio(s): Mr. Ahmer Syed is Vice President of Mechanical & Thermal Enginnering at Amkor Technology, USA heading the mechanical and thermal test and simulation group. Mr. Ahmer Syed has been involved in solder joint reliability predictions for almost 20 years and has published various technical papers dealing with solder joint reliability, finite element simulations, life prediction, and acceleration factors. He also chaired JEDEC task group to develop board level drop test method (JESD22-B111) and cyclic bend test method (JESD22-B113). He has strong background in solder damage mechanisms for thermal and mechanical loading conditions and has led Amkor technical group in Pb free solder alloy selection. He has also represented Amkor in various industry consortia and groups on package and board level reliability and Pb free solder.

10. Thermal Management of Hot Spots and 3D Chip Stacks
Course Leader(s) Avram Bar-Cohen University of Maryland Karl Geisler General Dynamics Advanced Information Systems

Course Objective: The rapid migration of microelectronics into nanoelectronics, with the consequent rise in transistor density and switching speed, has led to steep increases in die heat flux and growing concerns over the emergence of on-chip “hot spots”. 3D chip stacking can provide continuing “Moore’s Law” increases in package device density and reduced chip-to-chip interconnect delays, but these advantages come at the expense of higher heat densities and decreased physical access to the chip surfaces for heat removal. The application of on-chip high heat flux cooling techniques provides a most promising direction for the thermal management of 3D nanoelectronic packages and is the focus of this Professional Development course. Successful development of this cooling strategy requires the integration of thermal management principles and concepts into the design and development process from the earliest stages of chip design. Consequently, the course will begin with a brief review of the iNEMI and ITRS thermal roadmaps and a review of the thermal packaging technology options. Attention will then turn to thermal models of 3D chip packages and the application of emerging high flux, on-chip cooling techniques. Topics will include solid state thermoelectric coolers (both miniaturized and thin-film TECs), orthotropic spreaders, and direct liquid cooling.

Course Outline:
• Industry Roadmap for IC technology, 3D packaging, and thermal management
• Thermal management options – air, liquid, refrigeration
• Thermal models of 3D chip packages
• High-performance, orthotropic heat spreaders
• Solid-state refrigeration – miniaturized and thin-film TECs
• Dielectric liquid cooling – spray cooling, pool boiling, two-phase microgap coolers
• Wrap up: What have we learned?

Who Should Attend: This course is aimed at product managers, research staff, and packaging specialists involved in the design, development, optimization, and testing of advanced micro- and nanoelectronic products. Developers of advanced thermal management technology would also greatly benefit from this course.

Author Bio(s): Avram Bar Cohen is Distinguished University Professor and Chair of Mechanical Engineering at the University of Maryland, where he continues his research in the thermal management of micro/nano electronic and photonic systems. He is the co-author (with A.D. Kraus) of "Design and Analysis of Heat Sinks" (1995) and "Thermal Analysis and Control of Electronic Equipment" (1983) and has co-edited 13 books in this field. He has authored and co-authored some 250 Journal papers, Refereed Proceedings papers, and Chapters in books, and has delivered more than 50 Keynote, Plenary, and Invited Lectures at major technical Conferences and Institutions. He is currently the Editor-in-Chief of Transactions and a member of the Board of Governors of the IEEE CPMT Society. Bar-Cohen received the 2007 InterPack Achievement Award, the 2001 IEEE CPMT Society Outstanding Sustained Technical Contributions Award, the 2000 ASME Worcester Reed Warner Medal, and was earlier recognized with the ASME Heat Transfer Memorial Award and the ASME Curriculum Innovation Award in 1999 (with S. Bhavnani and Y. Joshi), the ASME/IEEE ITHERM Achievement Award in 1998, ASME Edwin F. Church Medal in 1994, and the THERMI Award from the IEEE/Semi-Therm Conference in 1997. He is a Fellow of ASME and of IEEE.

Karl Geisler is a Lead Mechanical Engineer at General Dynamics Advanced Information Systems in Bloomington, MN. Activities include product development, thermal packaging, and thermomechanical reliability of terrestrial, airborne, and space electronics. He has taught Heat Transfer in Electronic Equipment at the University of Minnesota, Twin Cities. Geisler has co-authored 2 archival journal papers, 13 conference papers, and 4 book chapters related to thermal analysis and design of electronics and boiling heat transfer. He received the PhD degree in Mechanical Engineering from the University of Minnesota in February of 2007 and is a member of ASME and the IEEE Components, Packaging and Manufacturing Technology (CPMT) Society.

11. Three-Dimensional (3D) Hyper-integration and Packaging of Micro-Nano-Systems
Course Leader(s) James Jian-Qiang Lu Rensselaer Polytechnic Institute

Course Objective: An overview of 3D hyper-integration and packaging of micro-nano-systems will be presented, including motivations, key alternative technologies, technology assessment, potential applications, and status towards commercialization. The major motivations discussed include miniaturization of micro-systems; performance increase in speed and data bandwidth due to massive small-sized inter-chip interconnects; heterogeneous system integration of variety of technologies; and lower manufacturing cost for specific applications using particular 3D platforms. In this course, 3D hyper-integration technologies are divided into 4 categories – 3D packaging, die-on-wafer assembly, transistor build-up, and wafer-level 3D. For 3D packaging, the ICs are packaged vertically in die-to-die, system-in-packaging (SiP) and package-on-package (PoP) fashions. The die-on-wafer assembly is similar to SoC approach, but with known-good-dies (KGDs) assembled on an IC wafer, then processed in wafer-level. In transistor build-up 3D, active devices are built-up over an IC wafer. In wafer-level 3D, different systems are first fabricated independently and then stacked and interconnected vertically. This course will discuss all these technologies, with emphasis on Through-Strata-Vias (TSVs), wafer-level 3D hyper-integration and potential applications. Sample designs and applications towards commercialization will also be presented. The issues associated with each technology category will be discussed, including integration architecture and design tools, yield and cost, thermal and mechanical constraints, and manufacturing infrastructure. Finally, future directions into micro/nano/electro-opto/bio system hyper-integrations including MEMS will be presented, showing 3D hyper-integration as a very promising emerging architecture for future computer, network, nanotech, and biotech applications.

Course Outline:
• Challenges of current ICs and packaging
• Why 3D Integration?
• Overview of 3D integration and packaging technologies
• Packaging-based 3D integration
• Die-on-wafer assembly 3D integration
• Transistor build-up 3D integration
• Wafer-to-wafer 3D hyper-integration: - Key unit processes; - Through-Silicon-Vias (TSV); - Oxide-to-oxide bonding; - Dielectric adhesive bonding; - Metal-to-metal bonding; - Metal/adhesive redistribution layer bonding
• Technology status, assessment and challenges/issues
• 3D-enabled designs and applications
• 3D Hyper-integration perspectives and technology projections
• Conclusions

Who Should Attend: Engineers, managers and executives involved in future R&D investments, assembly and product development of electronic packaging, and wanting fundamental understanding of 3D technologies, as well as the materials and equipment suppliers wanting to know about the existing and future 3D integration technologies and options, will greatly benefit from this course.

Author Bio(s): James Jian-Qiang Lu received his Dr. rer. nat. (Ph.D.) degree from Technical University of Munich in December 1995, and is currently an Associate Professor in Electrical Engineering at Rensselaer Polytechnic Institute (RPI), Troy, NY. At RPI, he worked with the Interconnect Focus Center (IFC) research program of 3D hyper-integration technology from 1999, and several other programs with focus on hyper-integration and micro-nano-bio interfaces for future chips. Prior to 1999, he held research and faculty positions at a number of universities in China, Germany and the United States. Dr. Lu has broad research experiences from micro-nano-electronics theory and design to materials, processing, devices, integration and packaging (e.g., GaAs, GaN and Si devices, novel FETs, terahertz electronics, carbon-nanotubes, and Si IC interconnects). He has authored/co-authored more than 200 publications in refereed journals, conferences or books, and given a number of invited presentations, seminars and short courses. Dr. Lu also served as technical chair, workshop chair, session chair, panelist and panel moderator, and conference committee members for many conferences. He is a senior member of IEEE (CPMT & EDS), a member of APS, MRS, ECS, and a member of IMAPS National Technical Committee (Chair of 3D Packaging). He received the 2008 IEEE CPMT Exceptional Technical Achievement Award in May 2008 “for his pioneering contributions to and leadership in 3D integration/packaging”.

12. Key Enabling Technologies for 3D IC Integration and WLP
Course Leader(s) John Lau HKUST

Course Objective: Moore's law has been the most powerful driver for the development of the microelectronic industry. This law emphasizes on lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC integration, which is a very complicate subject. It involves component and system designs, FAB, packaging, testing, and materials and equipment suppliers. The key enabling technologies for 3D IC integration and wafer-level Packaging (WLP) are, e.g., electrical, optical, thermal, and mechanical designs and tests, known good die (KGD), TSV (through silicon vias) with RDL (redistribution layers), wafer thinning and thin wafer handling, thin chip strength measurement and improving, low-cost lead-free microbump forming and assembly, low temperature C2W and W2W bonding, embedded WLP, hybrid SiP, optical PCB, and thermal management. In this lecture, all these enabling technologies will be discussed. Most of the materials are based on the technical papers published within the past 3 years by the instructor and others.

Course Outline:
• • Overview of 3D IC integration and packaging
• • TSV forming (DRIE and laser)
• • TSV dielectric, barrier, and seed-metal layers
• • TSV filling and CMP
• • Effects of TSV interposer on thermal performances on SiP
• • Effects of TSV interposer on mechanical performances on SiP
• • Stress sensor for thin-chip strength measurement
• • Wafer thinning and thin-wafer handling
• • Low-cost lead-free microbumps (≤25µm pitch): fabrication, assembly, characterization, and reliability
• • CMOS image sensor, 3D LED and 3D MEMS with TSV • 3D MEMS packaging with TSV
• • Low temperature (<200oC) C2W and W2W bonding
• • Thermal management (design charts and guidelines) for 3D stacked chips
• • Integrated liquid cooling solutions for 3D stacked modules
• • Hot spots in thin chips for 3D stacking
• • Supply chain for 3D IC integration and packaging
• • Critical issues in adopting TSV with RDL and 3D IC integration

Who Should Attend: If you (engineers and managers) are involved with any aspect of the electronics industry, you should attend this course. It is equally suited for R&D personals and scientists.

Author Bio(s): John Lau has been a visiting professor at HKUST (Hong Kong University Science & Technology) since January 2009. Prior to that, he was the Director of Microsystems, Modules & Components (MMC) Laboratory with Institute of Microelectronics (IME, Singapore) for 2 years and a Senior Scientist/MTS at HP/Agilent in US for more than 25 years. With more than 30 years of R&D and manufacturing experience, he has authored or co-authored more than 300 peer-reviewed technical publications and more than 100 book chapters, and given more than 250 presentations. He has authored and co-authored 16 textbooks on advanced packaging, solder joint reliability, and lead-free soldering and manufacturing. John earned his Ph.D. degree in theoretical and applied mechanics (University of Illinois) and three M.S. degrees in structural engineering, engineering physics and management science in North America. He is an elected ASME Fellow and has been an IEEE Fellow since 1994.

13. Polymers and nano-Composites for Electronic and Photonic Packaging : Recent Adv
Course Leader(s) C.P. Wong Georgia Tech Daniel Lu Daniel Lu Henkel Corporation

Course Objective: Polymers and nanocomposites are widely used in electronic and photonic packaging as adhesives, encapsulants, insulators, dielectrics, molding compounds and conducting elements for interconnects. These materials also play a critical role in the recent advances of low-cost, high performance Novel No Flow Underfills, Reworkable Underfills for Ball Grid Array (BGA), Chip Scale Packaging (CSP) , System in a Package(SIP)), Direct Chip Attach(DCA), Flip-Chip(FC) , Paper- thin IC and 3D Packaging, Conductive Adhesives( both ICA and ACA), Embedded Passives( high K polymer composites), nano particles and nano-functional materials such as CNTs, graphenes. It is imperative that both material suppliers, formulators and their users have a thorough understanding of polymeric materials and the recent advances on nano materials and their importance in the advances of the electronic packaging and interconnect technologies.

Course Outline:
• Fundamental of Polymers and Materials Science and Engineering
• Materials Needs for Next Generation of Electronic Packaging
• Novel Nanocomposites for Flip-chip Underfills Applications
• Recent advances on Nano Lead-free Alloys for High Performance Components Interconnects-
• Low-cost High Performance Lead-free Interconnect Materials and Processes
• Recent Advances on CNTs as Thermal Interface Materials(TIMs)
• Lotus Effect Coating for Self-cleaning Applications
• Fundamental understanding of conductive adhesives
• Recent advances on conductive adhesives and nano conductive adhesives

Who Should Attend: Engineers, scientists and managers involved in the design, process and manufacturing of IC electronic components and hybrid packaging, electronic material suppliers involved in materials manufacturing and research & development.

Author Bio(s): Prof. C. P. Wong is a Regents’ Professor and the Charles Smithgall Institute Endowed Chair at the School of Materials Science and Engineering at Georgia Institute of Technology(GT). He received his B.S. degree from Purdue University, and his Ph.D. degree(with Prof. Bill Horrocks) from the Pennsylvania State University. After his doctoral study, he was awarded a two-year postdoctoral fellowship with Nobel Laureate Professor Henry Taube at Stanford University. Prior to joining GT in 1996, he was with AT&T Bell Laboratories for many years and became an AT&T Bell Laboratories Fellow in 1992. His research interests lie in the fields of polymeric electronic materials, electronic, photonic and MEMS packaging and interconnect, interfacial adhesions, nano-functional material syntheses and characterizations. nano-composites such as well-aligned carbon nanotubes, grahenes, lead-free alloys, flip chip underfill, ultra high k capacitor composites and novel lotus effect coating materials. He received many awards, among those, the AT&T Bell Labs Fellow Award in 1992, the IEEE CPMT Society Outstanding Sustained Technical Contributions Award in 1995, the IEEE Third Millennium Medal in 2000, the IEEE EAB Education Award in 2001, the IEEE CPMT Society Exceptional Technical Contributions Award in 2002, the Georgia Tech Class 1934 Distinguished Professor Award in 2004, named holder of the Charles Smithgall Chair(one of the two GT Institute Chairs) in 2005, the GT Outstanding PhD Thesis Advisor Award, the IEEE Components, Packaging and Manufacturing Technology Field Award in 2006, the Sigma Xi’s Monie Ferst Award in 2007, the Society of Manufacturing Engineers’ Total Excellence in Electronic Manufacturing Award in 2008 and the IEEE CPMT David Feldman Award in 2009. He holds over 50 U.S. patents, and has published over 900 technical papers, co-authored and edited 10 books and is a member of the National Academy of Engineering since 2000.

Dr. Daniel Lu is the Technical Director of the R&D department of Electronics Materials Division of Henkel Corporation in Yantai, China. Daniel Lu received his MS and PhD degrees on Polymer Science and Engineering from Georgia Institute of Technology in 1996 and 2000, respectively. Prior to joining Henkel, Dr. Lu worked for the R&D department of Intel Corporation as a Sr. Scientist for 7 years. He also had worked for Lucent Technologies, Amoco’s Electronics Materials Division, and the Electronics Materials Group of National Starch and Chemical Company before. Dr. Lu has extensive experience in electronic packaging materials and processing. Dr. Lu received many awards including IEEE/CPMT Outstanding Young Engineer Award in 2004, ECTC best poster paper in 2007, Intel’s most patent filing in 2003-2007, Intel Divisional Recognition Awards in 2002, 2003, and 2007, Intel most patent granting of the year for 2006 and 2007, Best Graduate Student of the Year of Georgia Tech Packaging Research Center in 2000, and Best Paper of the Session of International Symposium and Exhibition on Advanced Packaging Materials in 2000. Dr. Lu published more than 40 technical papers, wrote chapters for four books, holds 52 US patents, and has more than 30 pending patent applications. Dr. Lu is a senior member of IEEE and an associate editor of IEEE Transactions on Advanced Packaging.

14. Flip Chip Fabrication and Interconnection
Course Leader(s) Eric Perfecto IBM

Course Objective: This course will cover all aspects of the flip chip technology. It will detail and compare the various UBM (electroplating, electroless plating and sputtering) and solder (plating, ball drop, C4NP, and solder screening) depositions methods, which are used in traditional single chip modules, multichip modules, chip scale packages and 3D applications (fine pitch). It will include process considerations when joining to laminate, PWB, ceramic and Si substrates. This course will detail the accelerated reliability tests currently used to qualify the flip chip connections, the failure types and the analytical tools used to identify defect root cause. Finally, it will cover the issues and solutions associated with Pb-free solder implementation, such as barrier consumption, Kirkendall void formation, BEOL cracking, etc. In less detail this course will cover alternate methods to solder connection, such as ACA, non –solder connections, etc, and the limitations of those technologies.

Course Outline:
• UBM selection, materials and wafer surface considerations
• Flip chip solder deposition processes including Cu-Post technology
• Fabrication issues, defect classification
• Pb and Pb-free solder considerations and their effect on UBM selection
• Implication of latest RoHS ruling
• Pb-free solder additives
• Assembly: Inspection, flux, reflow and underfill
• Fine pitch interconnection
• Wafer Level Packaging
• Flip chip solder structural testing
• Flip chip connection failure modes and root cause analysis
• Reliability testing including CPI issues such as device chip cracks
• Alternative methods for chip to substrate connection
• Technology limits and 3D applications

Who Should Attend: The targeted audience includes scientists, engineers and managers currently using flip chips or considering moving from wirebonding, as well as reliability, product or applications engineers who need a deeper understanding of flip chip advantages, limitations and failure mechanisms.

Author Bio(s): Eric Perfecto is a Senior Technical Staff Member at IBM, with 27 years of experience in the development of advanced packages at IBM Microelectronics. He holds an M.S. in Chemical Engineering from the University of Illinois and an M.S. in Operations Research from Union College. Eric developed and implemented multi-level thin films on top of ceramic substrates for high end servers. He is currently responsible for the UBM and Pb-free solder selection, implementation and yield improvements at IBM. His technical interests include chip joining, chip package interaction, electromigration, 3D, and design for manufacturing. Eric has published over 50 external papers, including two best Conference Paper Awards (2006 ESTC and 2008 ICEPT-HDP) and the 1994 Prize Paper Award from CMPT Trans. on Adv. Packaging. He holds over 30 US patents, and has been honored with two IBM Outstanding Technical Achievement Awards. Eric was the 57th ECTC General Chair in Reno, NV, and the Program Chair at the 55th ECTC. He has achieved senior member status from IEEE, IMAPS and Society of Plastic Engineers, and is a member of the Society of Hispanic Engineers. He is currently an elected member of the Board of Governors of the CPMT society of IEEE.

15. Package Failure Analysis - Failure Mechanisms and Analytical Tools
Course Leader(s) Rajen Dias Intel Corporation Deepak Goyal Intel Corporation

Course Objective: The technical course will provide an overview of the failure modes and mechanisms observed in the plastic packages. A brief introduction to the methodology of failure analysis of these packages will be described. Emphasis will be paid to the tools and techniques currently used and the future direction for the tools and techniques required for successful and timely failure analysis of next generation package technologies. A discussion on the strategies for use of these techniques and a flow chart for failure analysis will be included.

Course Outline:
• Package Technology – Trends, Drivers & Challenges
• Failure analysis challenges offered by package technology roadmap
• Overview of the failure modes and mechanisms observed in the organic packages
• Introduction to the methodology of failure analysis of organic packages
• Typical Failure analysis flow charts for opens and shorts
• Current Analytical Capabilities for Package Fault Isolation and Failure Analysis
• Strategies to use these techniques to identify failures and understand failure mechanisms
• Analytical Capabilities to support next generation packaging technologies

Who Should Attend: Engineers and technical managers who are involved in package technology development, reliability assessment of packages and failure analysis.

Author Bio(s): Dr Rajen Dias graduated with a MS and Ph.D in Materials Science from Lehigh University and joined Intel in 1984. He is currently a Principal Engineer in the Assembly Technology Development Quality & Reliability Group. His main areas of responsibility are in understanding failure modes and mechanisms of new package technologies and in developing next generation analytical tools and techniques for the failure analysis. He is currently the Vice General Chair of ECTC and a member of IEEE

Deepak Goyal graduated (Ph.D in Materials Science) from State University of New York, Stony Brook in 1990 and joined Intel as Failure analysis engineer. He is currently the Manager of the Assembly Technology Development Quality and Reliability Labs at Intel. His group supports the reliability stressing, materials and failure analysis for the Assembly Technology Development at Intel and next generation of analytical and reliability stress tools and techniques. He is a senior member of the IEEE

16. Digital Memory Design for Packaging Engineers
Course Leader(s) Moises Cases The Cases Group, LLC

Course Objective: The frequency of operation for digital systems has been increasing at a rapid pace over the years as the result of dramatic developments in semiconductor technology. This evolution is primarily due to device feature scaling and photo-lithographic equipment improvements. The memory subsystem is an important and integral part of digital systems since it provides the storage and communication facility for the central processor components in the system. As the processing speed increases, the behavior of the physical structures connecting the various components of the digital system becomes an important part of the system functionality and timing. This includes both the signal distribution integrity and the power distribution integrity. This course focuses on the memory system design as it relates to electronic packaging engineers and to signal and power integrity engineers. The course covers basic concepts in memory systems including architecture, organization and hierarchy, basic signal and power integrity concepts, an overview of current memory system specifications, typical memory topologies, and electrical modeling methodology and techniques.

Course Outline:
• Memory trends and road-maps
• Memory systems - architecture, hierarchy and organization
• Signal and power integrity concepts
• Typical memory system topologies and designs
• Double-data rate (DDR) memory timing and specifications
• Design methodology and techniques
• System design optimization - Signal and power distribution
• Design examples

Who Should Attend: This course is intended for both beginner and experienced packaging designers, electrical, thermal and mechanical engineers, electrical and computer engineering students and electronic packaging designers.

Author Bio(s):