Technical Program

Thursday, May 31, 2018

Session 13: Fan-Out and Interposer Interconnections
8:00 AM - 11:40 AM
Committee: Interconnections
Room: Harbor Island 1

Session Co-Chairs:

Katsuyuki Sakuma
IBM Corporation
T +1-914-945-2080
Jean-Charles Souriau
CEA Leti
T +33-4-38-78-98-16


1. 8:00 AM - Chip Stackable, Ultra-thin, High-flexibility 3D FOWLP (3D SWIFT) for Hetero-integrated Advanced 3D WL-SiP
WonMyoung Ki - Amkor Technology, Inc.
WonGeol Lee - Amkor Technology, Inc.
IlBok Lee - Amkor Technology, Inc.
InSu Mok - Amkor Technology, Inc.
WonChul Do - Amkor Technology, Inc.
Curtis Zwenger - Amkor Technology, Inc.
KangWook Lee - Amkor Technology, Inc.

2. 8:25 AM - Demonstration of Multi-layer Fine Pitch, Embedded Cu Trace with a Single Liquid Photosensitive Dielectric
Chun Hui Yu - Taiwan Semiconductor Manufacturing Company
L. J. Yen - Taiwan Semiconductor Manufacturing Company
C. Y. Hsieh - Taiwan Semiconductor Manufacturing Company
C. H. Hsieh - Taiwan Semiconductor Manufacturing Company
C. S. Liu - Taiwan Semiconductor Manufacturing Company
KC Yee - Taiwan Semiconductor Manufacturing Company
Doug C. H. Yu - Taiwan Semiconductor Manufacturing Company

3. 8:50 AM - Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging (FOWLP) with Large Chips and Multiple Re-Distributed Layers (RDLs)
John Lau - ASM
Ming Li - ASM
Margie Li - ASM
Iris Xu - JCAP
Tony Chen - JCAP
Zhang Li - JCAP
Kim Hwee Tan - JCAP
Rozalia Beica - DOW
Nelson Fan - ASM
Eric Kuah - ASM

4. 10:00 AM - Development of novel fine line 2.1 D package with organic interposer using advanced substrate-based process
wei-chung chen - Advanced Semiconductor Engineering, Inc
chiu-wen lee - Advanced Semiconductor Engineering, Inc
min-hua chung - Advanced Semiconductor Engineering, Inc
chaung-chi wang - Advanced Semiconductor Engineering, Inc
shang-kun huang - Advanced Semiconductor Engineering, Inc
yen-sen liao - Advanced Semiconductor Engineering, Inc
hung-chun kuo - Advanced Semiconductor Engineering, Inc
chen-chao wang - Advanced Semiconductor Engineering, Inc

5. 10:25 AM - Micro Bump System for 2nd Generation Silicon Interposer with GPU and High Bandwidth Memory (HBM) Concurrent Integration
JAESIK LEE - Nvidia Corporation
Chun Yang Lee - Nvidia Corporation
Chongho Kim - Nvidia Corporation
Shantanu Kalchuri - Nvidia Corporation

6. 10:50 AM - Low Cost Panel-based 1-2 Micron RDL technology with lower resistance than Si BEOL for large packages
Fuhan Liu - Georgia Institute of Technology
Hirokaza Ito - JSR Corporation
Rui Zhang - Georgia Institute of Technology
Bartlet DeProspo - Georgia Institute of Technology
Venky Sundaram - Georgia Institute of Technology
Rao Tummala - Georgia Institute of Technology

7. 11:15 AM - Advanced Anodic Aluminum Oxide Interposer Fabrication and 3D Embedded Inductors
Hsiang Yu Chan - University of California, Irvine
Mark Bachman - University of California, Irvine
Guann Pyng Li - University of California, Irvine