1. 8:00 a.m. - Large Die Flip Chip Packaging on Organic Substrates: The Role of Finite Element Analysis (FEA), Materials Characterization, Failure Analysis (FA) and Test Vehicles in Development Spins
Jason Goodelle, Ahmed Amin, Jeffery J. Gilbert, Christopher Horvath, Ed Nease, and Brian T. Vaccaro - Agere Systems

2. 8:25 a.m. - Differences in the Sub Processes of Ultra Fine Pitch Stencil Printing due to Type 6 and Type 7 Pb Free Solder Pastes used for Flip Chip
Gavin J. Jackson, Rajkumar K. Durairaj, and Ndy N. Ekere - University of Greenwich; Mike W. Hendriksen - Celestica; M.P.Y. Desmulliez and R.W. Kay - Heriot Watt University

3. 8:50 a.m. - Impact Properties of Flip Chip Interconnection using Anisotropically Conductive Film on the Glass and Flexible Substrate
Yiping P. Wu - City University of Hong Kong, Huazhong University of Science & Technology; M.O. Alam and Yan Cheong Chan - City University of Hong Kong; Bo Yi Wu - City University of Hong Kong. Huazhong University of Science & Technology

Refreshment Break: 9:15 - 10:00 a.m.

4. 10:00 a.m. - Accurate Predictions of Flip Chip BGA Warpage
Yuan Li - Altera

5. 10:25 a.m. - Bumpless Flip Chip Packages for Cost/Performance Driven Devices
Charles W.C. Lin, Sam C.L. Chiang, and T.K. Andrew Yang - Bridge Semiconductor

6. 10:50 a.m. - Viscoelastic Properties of Underfill for Numerical Analysis of Flip Chip Packages
Man Lung Sham and Jang Kyo Kim - Hong Kong University of Science and Technology; Joo Hyuk Park - Sejong University

7. 11:15 a.m. - Development of a 4 Layer Low Cost Flip Chip Packaging Technology
Anand Govind and Farshad Ghahghahi - LSI Logic

1. 8:00 a.m. - Solder Joint Reliability Model with Modified Darveaux's Equations for the Micro SMD Wafer Level Chip Scale Package Family
Li Zhang, Viraj Patwardhan, Luu Nguyen, and Nikhil Kelkar - National Semiconductor; Ram Sitaraman - State University of New York at Binghamton

2. 8:25 a.m. - Predictive Failure Model of Flip Chip on Board Component Level Assemblies
Jennifer Muncy, Theodore Lazarakis, and Daniel F. Baldwin - Georgia Institute of Technology

3. 8:50 a.m. - Effect of Package and Board Characteristics on Solder Joint Reliability of MicroStar BGA
Manjula Variyam, Tz Cheng Chiu, Vish Sundararaman, and Darvin Edwards - Texas Instruments

Refreshment Break: 9:15 - 10:00 a.m.

4. 10:00 a.m. - Optimal Choice of the FEM Damage Volumes for Estimation of the Solder Joint Reliability for Electronic Package Assemblies
Bart Vandevelde, Mario Gonzalez, and Eric Beyne - IMEC; G.Q. Zhang and Jo F.J.M. Caers - Philips

5. 10:25 a.m. - Guidelines for Structural and Material System Design of a Highly Reliable 3D Die Stacked Module with Copper Through vias
Naotaka Tanaka, Yasuhiro Yamaji, Tomotoshi Sato, and Kenji Takahashi - Association of Super Advanced Electronics Technologies (ASET)

6. 10:50 a.m. - Fatigue Life Models for SnAgCu and SnPb Solder Joints Evaluated by Experiments and Simulation
Andreas Schubert, Rainer Dudek, Ellen Auerswald, Astrid Gollhardt, Bernd Michel, and Herbert Reichl - Fraunhofer Institute for Reliability and Microintegration IZM

7. 11:15 a.m. - Damage Evolution in Sn62Pb36Ag2 Solder of a Chip Scale Package under a Monotonic Shear Stress
Sridhar Canumalla, S. Mathew, and S.K. Saha - Nokia Mobile Phones

1. 8:00 a.m. - Novel Multi Level Through Die Connections for Package to Chip Power and Ground Connections
Swaroop Kommera, Wayne Woods, and J. Peter Krusius - Cornell University

2. 8:25 a.m. - A Novel Electrically Conductive Wafer Through Hole Filled Vias Interconnect for 3D MEMS Packaging
C.S. Premachandran, Ranganathan Nagarajan, Chen Yu, Zhang Xiolin, and Chong Ser Chong - Institute of Microelectronics (IME)

3. 8:50 a.m. - IC Stacking Technology using Fine Pitch, Nanoscale through Silicon Vias
Silke Spiesshoefer and Leonard Schaper - University of Arkansas

Refreshment Break: 9:15 - 10:00 a.m.

4. 10:00 a.m. - Batch Fabrication of Through Wafer Vias in CMOS Wafers for 3 D Packaging Applications
Frank Engel Rasmussen and Ole Hansen - Technical University of Denmark; Matthias Heschel - Hymite

5. 10:25 a.m. - High Density Electroplating Bonding Interconnect Technology: Chip Packaging and High Aspect Ratio Passive Elements
Yeun Ho Joung and Mark G. Allen - Georgia Institute of Technology

6. 10:50 a.m. - High Density Packaging Technologies on Silicon Substrates
Miyuki Akazawa, Satoru Kuramochi, Tomoko Maruyama, Kouichi Nakayama, Atsushi Takano, and Masataka Yamaguchi - Dai Nippon Printing; Yoshitaka Fukuoka - Worldwide Electronic Integrated Substrate Technology

7. 11:15 a.m. - Using PDMS Microtransfer Molding (µTM) for Polymer Flip Chip
Cell K.Y. Wong, Otto C.T. Cheung, Bing Xu, and Matthew M.F. Yuen - Hong Kong University of Science and Technology

1. 8:00 a.m. - Improvement in the Properties of Sn Zn Eutectic Based Pb Free Solder
Kwang Lung Lin, Hui Min Hsu, and Chia Ling Shi - National Cheng Kung University; Kang I Chen - Tung Fang Institute of Technology

2. 8:25 a.m. - Pb Free Bumping by Alloying Electroplated Metal Stacks
Hirokazu Ezawa, Masahiro Miyata, Masaharu Seto, and Soichi Honma - Toshiba Semiconductor

3. 8:50 a.m. - New Fluxless Bonding Process in Air using Sn Bi with Au Cap
Dongwook Kim and Chin C. Lee - University of California, Irvine

Refreshment Break: 9:15 - 10:00 a.m.

4. 10:00 a.m. - Bulk Solder and Solder Joint Properties for Lead Free 95.5Sn 3.8Ag 0.7Cu Alloy
John H.L. Pang, B.S. Xiong, C.C. Neo, X.R. Zhang, and T.H. Low - Nanyang Technological University

5. 10:25 a.m. - Mechanical Tensile Fracture Behaviors of Solid State Annealed Eutectic SnPb and Lead Free Solder Flip Chip Bumps
Jin Wook Jang, Ananda De Silva, Jong Kai Lin, and Darrel Frear - Motorola

6. 10:50 a.m. - A Reliability Comparison of Electroplated and Stencil Printed Flip Chip Solder Bumps Based on UBM Related Intermetallic Compound Growth Properties
Jing Feng Gong, Guo Wei Xiao, Philip C.H. Chan, Ricky S.W. Lee, and Matthew M.F. Yuen - Hong Kong University of Science and Technology

7. 11:15 a.m. - 3D Large Deformation and Nonlinear Stress Analyses of Tin Whisker Initiation and Growth on Lead Free Components
John H. Lau - Agilent Technologies; Stephen H. Pan - Optimal; Chen Xu - Enthone

1. 8:00 a.m. - Experimental and Modeling Analysis of the Reliability of the Anisotropic Conductive Films
Chunyan Yin, Hua Lu, and Chris Bailey - University of Greenwich; Yan Cheong Chan - City University of Hong Kong

2. 8:25 a.m. - Delamination Control in Electronic Packaging Using the Energy Method
Haibo B. Fan, Hon Bun Tang, Matthew M.F. Yuen, and Philip C.H. Chan - Hong Kong University of Science and Technology

3. 8:50 a.m. - Mechanical Characterization and Modeling of Low Dielectric Constant SiLK Films using Nano Indentation: Time and Temperature Effects
Jaap den Toonder, Auke van Dijken, Johan Beijer, and Kouchi Zhang - Philips; Viktor Gonda and Leo J. Ernst - Delft University of Technology; Joost Waeterloos - Dow

Refreshment Break: 9:15 - 10:00 a.m.

4. 10:00 a.m. - Interfacial Fracture Analysis of Underfill Delamination and Flip Chip Reliability Optimization
Charlie J. Zhai, Sidharth Sidharth, Richard C. Blish II, Raj Master, and Srinivasan Parthasarathy - Advanced Micro Devices

5. 10:25 a.m. - Optimization and Stochastic Procedures for Robust Design of Photonic Packages with Applications to a Generic Package
Satish Radhakrishnan and Ganesh Subbarayan - Purdue University; Luu Nguyen and William Mazotti - National Semiconductor

6. 10:50 a.m. - Effect of Packaging on Interfacial Cracking in Cu/ Low k Damascene Structures
Guotao Wang and Paul S. Ho - University of Texas Austin; Steven Groothuis - Micron Technology Texas LLC

7. 11:15 a.m. - Analytical Solution for Moisture Induced Interface Delamination in Electronic Packaging
Xuejun Fan, G.Q. Zhang, and W.D. van Driel - Philips; Leo J. Ernst - Delft University of Technology

1. 8:00 a.m. - Development of a Web based Course on Lead Free Solders for Electronics Packaging
Johan Liu and Cristina Anderson - Chalmers University of Technology

2. 8:25 a.m. - Mechanical Properties of Packaging Materials The Need and a Strategy for an Educational Module
Steffen Wiese and Klaus Juergen Wolter - Dresden University of Technology

3. 8:50 a.m. - Flip Chip Packaging Interconnect Technology and Reliability
Xiaoling He - University of Wisconsin, Milwaukee

Refreshment Break: 9:15 - 10:00 a.m.

4. 10:00 a.m. - Multimedia for MEMS Technologies and Packaging Education
Gabor Harsányi, Gergely Ballun, Peter Bojta, Peter Gordon, and H. Sántha - Budapest University of Technology and Economics (BUTE)

5. 10:25 a.m. - Development of Graduate Level Optoelectronics Packaging Courses at at San Jose State University
Guna Selvaduray and Joseph Becker - San Jose State University

6. 10:50 a.m. - Educational Development for Mixed Signal Design and Test
Kimberly Newman and Gerald Edelstein - University of Denver

7. 11:15 a.m. - International Web Course on Mixed Signal IC Test
Bruce C. Kim, Vijay Varadarajan, and Se Hyun Park - Arizona State University

1. 1:30 p.m. - The Optical Challenges in Next Generation Networks
Michael Socher - Siemens Information and Communication Networks

2. 1:55 p.m. - Tunable Optical Filters for Dynamic Networks
Kevin Hsu and Bob Cormack - Micron Optics

3. 2:20 p.m. - Micro Electro Mechanically Tunable Two Chip VCSELs for 1.55 µm
Frank Riemenschneider, Hubert Halbritter, and Peter Meissner - Technische Universität Darmstadt; Isabelle Sagnes and Clementine Symonds - LPN CNRS; Gerhardt Böhm, Markus Maute, and Markus Christian Amann - Technische Universität München

Refreshment Break: 2:45 - 3:30 p.m.

4. 3:30 p.m. - Performance and Reliability of Widely Tunable Laser Diodes
T. Wipiejewski, Y. A. Akulova, G. A. Fish, P. C. Koh, C. Schow, P. Kozodoy, A. Dahl, S. Nakagawa, M. Larson, M. Mack, T. Strand, C. Coldren, E. Hegblom, S. Penniman, L. A. Coldren- Agility Communications

5. 3:55 p.m. - Integrated Tunable Transmitters for 10Gb/s Long Haul DWDM Applications
Jon Hall, Colin Edge, Fred Randle, Steve Pope, Jim Fraser, Jason Loosely, E.M. Kimber, and P. Firth - Bookham Technology

6. 4:20 p.m. - WDM Power Level Monitor with Micro Pyramid Mirrors Formed in Arrayed Optical Waveguide
Hikaru Kouta, Mikio Oda, Taro Kaneko, and Yutaka Urino - NEC; Tadahiko Hanada - NEC FiberOptech

7. 4:45 p.m. - Development of Internal Wavelength Lockers for Tunable Laser Applications
Hongtao Han, Barney Hammond, Robert Boye, Bingzhi Su, Jay Mathews, Bob TeKolste, Alvaro Cruz, Doug Knight, Bill Padgett, and Dave Aichele - Digital Optics

1. 1:30 p.m. - Microstructural and Performance Implications of Gold in Sn Ag Cu Sb Interconnections
Weiqun Peng, Steven Dunford, Puligandla Viswanadham, and Stephen Quander - Nokia Mobile Phones

2. 1:55 p.m. - Characterization of Solder Joint Electromigration for Flip Chip Technology
Jong Kai Lin, Jin Wook Jang, and Jerry White - Motorola

3. 2:20 p.m. - Tin Whisker Formation Results, Test Methods and Countermeasures
Marc Dittes - Infineon Technologies; Pascal Oberndorff - Philips; Luc Petit - STMicroelectronics

Refreshment Break: 2:45 - 3:30 p.m.

4. 3:30 p.m. - Thermo Mechanical Fatigue Reliability of Pb Free Ceramic Ball Grid Arrays: Experimental Data and Lifetime Prediction Modeling
Mukta Farooq, Lewis Goldmann, Gregory Martin, Charles Goldsmith, and Christian Bergeron - IBM

5. 3:55 p.m. - Advances in Fne Pitch Lead Free Assembly Process
Ravi Doraiswami, Sandeep Sankararaman, Woopoung Kim, Jing Li, Zhuqing Zhang, Piyush Gupta, Manish Borkar, Raghav Madhavan, Vinu Govind, Suna Choi, Ankur O. Aggarwal, Y.Sun, Lianhua Fan, Venky Sundaram, Madhavan Swaminathan, C.P. Wong, Rao R. Tummala - Georgia Institute of Technology; and Kensuke Nakanishi - Harima Chemicals

6. 4:20 p.m. - Fluxless Flip Chip Technique with Sn rich Au/Sn Solder Bumps
Dongwook Kim and Chin C. Lee - University of California, Irvine; Witold M. Sokolowski - Jet Propulsion Laboratories

7. 4:45 p.m. - Fracture Toughness of Cu Sn Intermetallic Compounds in Electronic Packages
Zhong Chen and Tommy Cahyadi - Nanyang Technological University; Ming Li - Chinese University of Hong Kong; Bavani Balakrisnan and Chan Choy Chum - Institute of Materials Research and Engineering

1. 1:30 p.m. - Room Temperature Bonding of Ultra Fine Pitch and Low Profiled Cu Electrodes for Bump Less Interconnect
Akitsu Shigetou, Toshihiro Itoh, Katsuya Okumura, and Tadatomo Suga - University of Tokyo; Mie Matsuo and N. Hayasaka - Toshiba

2. 1:55 p.m. - Improvement in WL CSP Reliability by Wafer Thinning
Li Wetz, Jerry White, and Beth Keser - Motorola

3. 2:20 p.m. - An Analysis of the Reliability of a Wafer Level Package (WLP) using a Silicone Under the Bump (SUB) Configuration
Mario Gonzalez, Bart Vandevelde, Mathieu Vanden Bulcke, Christophe Winters, and Eric Beyne - IMEC; Yeong J. Lee, Lyndon Larson, Brian R. Harkness, Mustafa Mohamed, Herman Meynen, and Eric Vanlathem - Dow Corning

Refreshment Break: 2:45 - 3:30 p.m.

4. 3:30 p.m. - Multi Chip Memory Module with a Flip Chip On Chip Structure and an Optional Center Via Hole for Underfill Dispensing
S.W. Ricky Lee, Yat Kit Tsui, and Raymond So - Hong Kong University of Science and Technology; Le Luo - Shanghai Institute of Microsystems and Information Technology (SIMIT)

5. 3:55 p.m. - High Speed SMT Compatible Dispenseless Underfill Process for CSP BGA Flip Chip Assembly
Jian Zhang and Daniel F. Baldwin - Georgia Institute of Technology

6. 4:20 p.m. - Processability and Electrical Characteristics of Glass Substrates for RF Wafer Level Chip Scale Packages
Alexander Polyakov, Saoer Sinaga, Marian Bartek, Behzad Rejaei, and Joachim Burghartz - Delft University of Technology; Paulo Mendes and Jose Correia - University of Minho

7. 4:45 p.m. - Highly Reliable and Low Cost Multi Chip Module Composed of Wafer Process Packages
Yasuhiro Naka, Naotaka Tanaka, and Takahiro Naito - Hitachi

Electrical Modeling of Global Interconnects with Electromagnetic Accuracy
Andreas Cangellaris and Aosheng Rong - University of Illinois at Urbana Champaign

Accurate HSPICE Modeling of Arbitrary Package Geometries Using Transmission Line Equivalent Techniques
Timothy Budell, Paul Clouser, and Eric Tremble - IBM Corporation; Brian Welch - Cornell University

Investigation of the Impact of Conductor Surface Roughness on Interconnect Frequency Dependent Ohmic Loss
Andreas Cangellaris and Leonid Proekt - University of Illinois at Urbana Champaign

Waveguide Type Shield Model for LSI Chip that Reduces EMI and Temperature
Hideo Kikuchi - Association of Super Advanced Electronics Technologies; Osamu Ibaragi - Association of Super Advanced Electronics Technologies (ASET)

3GHz Through Hole Signal Via Model Considering Power/Ground Plane Resonance Coupling and Via Neck Effect
Jun So Pak and Joungho Kim - Korea Advanced Institute of Science and Technology (KAIST)

Extension of the Hybrid Phase Pole Macromodel to Frequency Dependent Lossy Transmission Lines
Bing Zhong, Steven Dvorak, and John Prince - University of Arizona

Accurate Modeling of Multilayer Packaging Structures with Multiple Ground Planes Including Metal and Dielectric Loss Characteristics
Edan Dalton, Nathan Bushyager, and Manos Tentzeris - Georgia Institute of Technology; Marco Kunze and Wolfgang Heinrich - Ferdinand Braun Institut für Höchstfrequenztechnik

Multi channel Optical Interconnects for Short Reach Applications
David Dolfi - Agilent Technologies, Inc.

10 Gbit/s per Channel Parallel Optical Transmitter and Receiver Modules for High Capacity Interconnects
Masato Shishikura, Takuma Ban, Hirokazu Ichikawa, Tatemi Ido, Makoto Takahashi, koji Nakahara, Etsuko Nomoto, Yasunobu Matsuoka, Kyosuke Ishikawa, Masahiro Ito, Ryoji Takeyari, and Hirohisa Sano - Hitachi, Ltd.

High Speed Optical Interconnection using Embedded PDs on Electrical Boards
Sang Yeon Cho, Jeff Hall, Ananthasayanam Chellappa, Nan Jokerst, and Martin Brooke - Georgia Institute of Technology

Planar Glass Wave Guides for High Performance Electrical Optical Circuit Boards (EOCB) The Photonic Layer Concept
Henning Schröder - Fraunhofer Institute for Reliability and Microintegration IZM; Norbert Arndt Staufenbiel - Brandenburgische Technische Universität Cottbus; Manfred Cygon - Isola AG

Performance Comparison of Parallel Optical Interconnects for Enterprise Servers
Casimer DeCusatis - IBM Corporation; Rob Atkins - Princeton University

Status and Progress of Optical Backplane Solutions for Terabit DXCs
Robert Fuerst and Axel Beier - Infineon Technologies

Opto Electonic Backplane Technology for Cost Effective Bandwidth Management
Michael Meis - 3M