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Technical
Program
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| MAY
30, 2003 |
Session
26: 3D Packaging Technologies
8:00 a.m. 11:40 a.m.
Committees: Advanced Packaging and Interconnections
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Session
Co-Chairs:
Jeffrey
A. Knight - IBM Corp.
Tel: +1 607 757 1015
Fax: +1 607 757 1860
Email: knightj@us.ibm.com
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S.
W. Ricky Lee - Hong Kong University of Science
& Technology
Tel: +852 2358 7203
Fax: +852 2358 1543
Email: rickylee@ieee.org |
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Chip to Wafer Stacking
Technology for 3D System Integration
Armin Klumpp, Reinhard Merkel, Robert Wieland,
and Peter Ramm - Fraunhofer Institute for Reliability
and Microintegration IZM
Ultra High Density
3D Chip Stacking Technology
Kazumasa Tanida, Mitsuo Umemoto, Yoshihiro Tomita,
Yoshihiko Nemoto, Masamoto Tago, Tatsuya Ando,
and Kenji Takahashi - Association of
Super Advanced Electronics Technologies (ASET)
Planar Metallization
Interconnected 3 D Multi chip Module
Zhenxian Liang - CPES, Virginia Tech; J. D. Van
Wyk - Virginia Tech
Design and Stacking
of an Extremely Thin Chip Scale Package
Akito Yoshida - Amkor Technology, Inc.; Kazuo
Ishibashi - Nokia Mobile Phones
Stacked Multichip
Package with Plastic Ball Vertical Interconnections
Jani Miettinen, Jarmo Tanskanen, and Eero Ristolainen
- Tampere University of Technology
Three Dimensional
System in Packaging Technology
Takuya Sugiyama, Yano Yuji, Seiji Ishihara, Yasuki
Fukui, Hiroyuki Juso, Koji Miyata, Yoshiki Sota,
and Tomoshi Kimura - Sharp Corporation
Development of Distributed
Sensing Systems of Autonomous Micro Modules
John Barton, Kieran Delaney, and Cian Ó
Mathúna - NMRC; Joseph Paradiso and Ari
Benbasat - MIT Media Lab
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Session
27: Novel Interconnections
8:00 a.m. 11:40 a.m.
Committee: Interconnections
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Session
Co-Chairs:
Dennis
Olsen - Consultant
Tel: +1 480 994 9926
Fax: +1 480 994 8013
Email: d.olsen@ieee.org
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David
McCann - Amkor Technology, Inc.
Tel: +1 480 821 5000 5029
Fax: +1 480 821 2389
Email: dmcca@amkor.com |
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Development
of a Novel Technology for Building Flexible and
Wearable Integrated Systems
Thomas Healy, Alan Mathewson, John Alderman, and
Julie Donnelly - NMRC
New Assembly Technologies
for Textile Transponder Systems
Christine Kallmayer - Fraunhofer Institute for Reliability
and Microintegration IZM; Rubin Pisarek and Sven
Cichos - TU Berlin; Andreas Neudeck and Sabine Gimpel
- TITV
Multi Layer Flexible Substrate for MCM Module
Hyuek Jae Lee and Jin Yu - Korea Advanced Institute
of Science and Technology (KAIST)
A Novel Technology for Stacking the Microvias on
the Printed Circuit Board
Fuhan Liu, George White, Venky Sundaram, Ankur Aggarwal,
Dean Sutter, and Rao Tummala - Georgia Institute
of Technology
Laser Ablation as an Enabling Technology for Opto
Boards
Peter Van Daele, Geert Van Steenberge, Peter Geerinck,
Steven Van Put, and Maarten Cauwe - IMEC Ghent University
Demonstration of On PCB Optical Interconnection
Using Surface Mount Packages and Polymer Waveguide
Yuzo Ishii, Tsuyoshi Hayashi, and Hideyuki Takahara
- NTT
Embedded Optical Interconnections on Printed Wiring
Boards
Takeshi Suzuki, Toshihisa Nonaka, Sang Yeon Cho,
and Nan Jokerst - Georgia Institute of Technology
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Session
28: Reliability Issues in Polymers and Interfaces
8:00 a.m. 11:40 a.m.
Committee: Quality & Reliability
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Session
Co-Chairs:
Charles
Zhang - Intel Corporation
Tel: +1 480 552 0453
Fax: +1 480 554 7171
Email: charles.zhang@intel.com
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Ephraim Suhir - U. of IL at Chicago and
ERS Co.
Tel: +1 650 969 1530
Fax: 650 968 4611
Email: suhire@aol.com
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Prediction
of Delamination in Bi material System Based on Free
Edge Energy Evaluation
Haibo Fan and Mathew M. F. Yuen - Hong Kong University
of Science and Technology; Ephraim Suhir - University
of Illinois at Chicago, and ERS Co.
A Modified Button Shear Method of Measuring Adhesion
Strength of Polymer Metal Interfaces Encountered
in IC Packages
Andrew Tay and Jyh Siong Phang - National University
of Singapore; Ee Hua Wong and Rajoo Ranjan - Institute
of Microelectronics (IME)
Failure Analysis of
Full Delamination on the Stacked Die Leaded Packages
Tingyu Lin, Yu Feng Yao, Zheng Peng Xiong, Tok Lane,
ZeYan Yu, Njoman Budi, and K. H Chua - Agere Systems
Prediction of Moisture
Induced Failures in Flip Chip on Flex Interconnections
with Non Conductive Adhesives
Jo Caers and Xiujuan Zhao - Philips Electronics
Singapore; Ee Hua Wong, Xiao Wu Zhang, Chu Kuen
Ong, and Ranjoo Ranjan - Institute of Microelectronics
(IME)
Evaluation of RF PA
Module Reliability
Robert Darveaux, Jicheng Yang, and Ahmer Syed -
Amkor Technology, Inc.
Reliability Study for Low Cost Semiconductor Packaging
for Long Life Applications
Elie Awad, Francisco Vicenty, and Niki Spencer -
IBM Corporation
Reliability Evaluation Structures for Stacked Thin
Dice Packaging
Paivi Karjalainen, Jarmo Tanskanen, and Eero Ristolainen
- Tampere University of Technology
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Session
29: Interconnect Metallurgies
8:00 a.m. 11:40 a.m.
Committee: Materials & Processing
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Session
Co-Chairs:
Rajen
Chanchani - Sandia National Labs
Tel: +1 505 844 3482
Fax: +1 505 844 7011
Email: chanchr@sandia.gov
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Eric
Perfecto - IBM Microelectronics
Tel: +1 845 894 4400
Fax: +1 845 892 6208
Email: perfecto@us.ibm.com
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Comparison
of Interfacial Reactions and Reliabilities of
Sn3.5Ag, Sn4.0Ag0.5Cu, and Sn0.7Cu Solder Bumps
on Electroless Ni P UBMs
Young Doo Jeon and Kyung Wook Paik - Korea Advanced
Institute of Science and Technology (KAIST); Adreas
Ostmann and Herbert Reichl - Fraunhofer Institute
for Reliability and Microintegration IZM
Investigation of Electroplating Ni UBM for Pb
Free Solders
Shu Ming Chang - Industrial Industrial Technology
Research Institute (ITRI); Ruoh Huey Uang, Dau
Chi Liou, Hsu Tien Hu, Kuo Chuan Chen, Yu Fang
Chen, and Yu Hua Chen - Industrial Technology
Research Institute (ITRI)
Growth and Selection of
Intermetallic Species in Sn Ag Cu no Pb Solder
Systems Based on Pad Metallurgies and Thermal
Histories
Lawrence Lehman and Eric Cotts - State University
of New York at Binghamton
UBM Integrity Studies on
Copper/Low k Dielectrics for Fine Pitch Flip Chip
Packaging
Seung Wook Yoon, Vaidyanathan Kripesh, Wai Kwan
Wong, Xian Tong Chen, Dong Gui, and K. Iyer Mahadevan
- Institute of Microelectronics (IME); Chayong
Li - Institute of Microelecttronics (IME); Ignatius
J Rasiah - Honeywell
Investigation of Co UBM for Direct Flip Chip Bumping
on Cu/lowK Dies
Riet Labie, Eric Beyne, and Petar Ratchev - IMEC
Effects of Antimony on the Growth of Intermetallic
Compounds in Sn Ag Cu Pb free Solder Joints
Guoyuan Li and Binling Chen - Nanyang Technological
University
Interfacial Reaction of Eutectic AuSi Solder with
Si (100) and Si (111) Surfaces
Jin Wook Jang, Scott Hayes, Jong Kai Lin, and
Darrel Frear - Motorola, Inc.
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Session
30: Electrical Characterization and Validation
8:00 a.m. 11:40 a.m.
Committee: Modeling & Simulation
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Session
Co-Chairs:
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Model to
Hardware Correlations in the Design of a 50Gb/s
Package
Lei Shan, Mounir Meghelli, Alexander Rylyakov, Jean
Trewhella, and Modest Oprysko - IBM Corporation
Analysis of RF Flip
chip On chip Inductance with Novel Measurement Technology
Gye An Lee and De Flaviis Franco - University of
California, Irvine; Mohamed Megahed - Skyworks,
Inc.
Broadband Characterization of Package Dielectrics
Henning Braunisch and Dong Ho Han - Intel Corporation
High Frequency Modeling
and Characterization of Pin and Land Grid Array
Sockets
Dong Ho Han, Victor Prokofiev, Leigh Wojewoda, Thomas
Ruttan, and Polka Lesley - Intel Corporation
Electrical Modeling
and Characterization of Packaging Solutions Utilizing
Lead Free Second Level Interconnects
Daniel O'Connor, Harvey Hamel, and Christopher Spring
- IBM Corporation
Simple and Accurate
Determination of Complex Permittivity and Skin Effect
of FR4 Material in Gigahertz Regime
Karl Bois, Brian Kirk, Michael Tsuk, and David Quint
- Hewlett Packard
Effect of Decoupling
Capacitors on Signal Integrity in Applications With
Reference Plane Change
Junho Lee, Albert C. W Lu, Wei Fan, and Lai L. Wai
- Singapore Institute of Manufacturing Technology
(SIMTech); Joungho Kim - Terahertz Media and System
Lab., KAIST
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Session
31: Low Cost Manufacturing of Optoelectronics
1:30 p.m. 5:10 p.m.
Committee: Optoelectronics
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Session
Co-Chairs:
James
E. Watson - 3M
Tel: +1 651 733 3890
Fax: +1 651 736 4137
Email: jewatson@mmm.com
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Andrew
Shapiro - UC Irvine
Tel: +1 949 824 8086
Fax: +1 949 824 2541
Email: aashapiro@aol.com
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Micro Photonic
Integrated Circuits for Low Cost Optical Systems
Waguih Ishak - Agilent Technologies, Inc.
High Performance and
Highly Functional Semiconductor Optical Amplifiers
Based on Hybrid and Monolithic Integration
Mario Dagenais - a; Peter S. Heim, Stewart Wilson,
Simarjeet Saini, Dennis Bowler, Timothy Horton,
Yimin Hu, Anthony Yu, Dennis Stone, and Vince Luciani
- Quantum Photonics, Inc.
Automated Assembly
and Packaging of Hybrid Optical Modules
Henrik Madsen, Lior Shiv, and Matthias Heschel -
Hymite A/S; Gordon Elger, Andreas Hase, and Jochen
Kuhmann - Hymite GMBH
Quasi hermetic Photonic
Packages with Polymer Sealants in a Central Office
Environment
Frank Xu - Chorum Technologies
Direct coupling Fiber
Retention Using Laser Soldering: Technical and Economic
Benefits
Cathal Flanagan, Scott Trask, and Randy Heyler -
Newport Corporation
High Coupling Efficiency
Actively Aligned Laser Modules Using Micro Heaters
and Pre Compensation
Madhumita Datta and Mario Dagenais - University
of Maryland
Silicon Microlens on
V groove Platform for Low Cost and High Performance
Optical Modules
Daisuke Shimura, Masahiro Uekawa, Kyoko Kotani,
Yoshinori Maeno, Hironori Sasaki, and Takeshi Takamori
- Oki Electric Industry Co., Ltd.
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Session
32: Wire Bonding
1:30 p.m. 5:10 p.m.
Committee: Interconnections
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Session
Co-Chairs:
Rajen
Dias - Intel Corp.
Tel: +1 480 554 5202
Fax: +1 480 554 7171
Email: rajen.c.dias@intel.com
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Mark
V. Brillhart - Cisco Systems Inc.
Tel: +1 408 525 7466
Fax: +1 408 527 8535
Email: mbrillha@cisco.com
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Novel Method
of Separating Probe and Wire Bond Regions without
Increasing Die Size
Tu Anh Tran, Chu Chung Lee, Tu Anh Tran, Bill
Williams, and Jody Ross - Motorola, Inc.
Dynamic and Quasi Static
Three Dimensional Simulation of Wire Looping Process
in Wirebonding
Andrew Tay and Beng Hung Ng - National University
of Singapore; Soon Huat Ong - National Semiconductor
Singapore
Wire Looping Optimization
in Fine Pitch Wire Bonded Staggered Pad Devices
Tu Anh Tran, Tu Anh Tran, Lois Yong, and Fuaida
Harun - Motorola, Inc.
Reliability of Wirebond
Over Active Circuitry for 0.13um CMOS Technology
Kevin Hess, Susan Downey, James Miller, David
Wontor, Geoffrey Hall, Willson Ng, and Lei Mercado
- Motorola, Inc.
Wirebonding Problems on Probe Marks and Possible
Solutions
Wolfgang Sauter - IBM Corporation; Toyohiro Aoki,
Takashi Hisada, and Hiromitsu Miyai - IBM Japan;
Kevin Petrarca and Jennifer Power - IBM USA; Frederic
Beaulieu - IBM Canada
Improving the Deflection of Wire Bonds in Stacked
Chip Scale Package (CSP)
Yufeng Yao, Tinyu Lin, and Simon Chua - Agere
Systems Singapore Pte Ltd
Design Optimization of Wire Bonding for Advanced
Packaging Applications
C. W Lu and Lai L. Wai - Singapore Institute of
Manufacturing Technology (SIMTech); Wei Fan -
Singapore Institute of Manufacturing Technology
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Session
33: Adhesives
1:30 p.m. 5:10 p.m.
Committee: Materials & Processing
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Session
Co-Chairs:
Johan
Liu - Chalmers University of Technology
Tel: +46 31 706 6294
Fax: +46 31 706 6289
Email: johan.liu@me.chalmers.se
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Jim
Morris - Portland State University
Tel: +1 503 725 9588
Fax: +1 503 725 3807
Email: j.e.morris@ieee.org
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Effect
of Sacrificial Anodic Fillers on Contact Resistance
Stability of Electrically Conductive Adhesives onto
Lead Free Alloy Surfaces
Haiying Li, Kyoung Sik Moon, and C. P. Wong - Georgia
Institute of Technology
Investigation of Conductive
Adhesive Bonding using UV Curable ACFs at Different
Curing Conditions
Ka Ka Lee, Sai Choo Tan, Yan Cheong Chan, Nin Hong
Yeung, and Kai Kay Chan - City University of Hong
Kong
Thermal Conductivity and RF
Signal Transmission Properties of Ag Filled Epoxy
Resin
Tadashi Kimura, Tsukasa Nakai, Haruo Ishikawa, Chizuko
Ooyama, Keiichi Oosawa, and Shigeru Kohinata - Sumitomo
Metal Mining Co., Ltd.
A Reworkable Epoxy Resin for Isotropically Conductive
Adhesive
Haiying Li and C. P. Wong - Georgia Institute of
Technology
Flip Chip Interconnection
using Anisotropic Conductive Adhesives for RF and
High Frequency Applications
Myung Jin Yim, In Ho Jung, Ki Joong Kim, Jin Sang
Hwang, Jin Gu Kim, and Jin Yong Ahn - Telephus,
Inc; Woonsung Kwon and Kyung Wook Paik - Korea Advanced
Institute of Science and Technology (KAIST)
Improvements in the Reliability
and Manufacturability of an Integrated RF Power
Amplifier Module System In Package, via Implementation
of Conductive Epoxy Adhesive for Selected SMT components
Daniel Cavasin, Ken Brice Heames, and Anwar Arab
- Motorola, Inc.
Thermo mechanical Behavior of a Novel Light Modulator
Zhimin Mo, Shiming Li, and Johan Liu - Chalmers
University of Technology; Helge Kristiansen - SINTEF
Electronics and Cybernetics; Morten Eliassen - Photonyx
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Session
34: System Design Electrical Issues
1:30 p.m. 5:10 p.m.
Committee: Modeling & Simulation
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Session
Co-Chairs:
Ravi
Kaw - Agilent Technologies, Inc.
Tel: +1 408 345 8893
Fax: +1 408 345 8088
Email: ravi_kaw@agilent.com
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George
A. Katopis - IBM
Tel: +1 914 435 6719
Fax: +1 914 435 1593
Email: katopis@us.ibm.com
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Modeling
The Performance Of Embedded Gridded Plane Structures
In LTCC
Guang Chen and Kathleen Virga - University of Arizona;
Gert Winkler - Technische Universität Ilmenau,
Ilmenau, Germany; John Prince - ECE Dept, University
of Arizona
Substrate Design Optimization
for High Speed Links
Daniel de Araujo - IBM Corporation; Moises Cases
- IBM xSeries eServer; Nam Pham - IBM Corporation
eServer; Barry Rubin - IBM Research
Dependence of Bus Performance
on the Choice of BGA Package used for a Formatter
Chip in a Printer Card
Ravi Kaw, Robert Batey, Michael Kelly, and Joseph
Casprowiak - Agilent Technologies, Inc.
PentiumTM 4 Processor
Package Design and Development
Altaf Hasan, Ajit Sathe, Ram Viswanath, and Dustin
Wood - Intel Corporation
Split Ground Effect
of Electronic Package on the Input level of High
Speed DRAM
Jongjoo Lee, Junghwan Choi, and Dong Ho Lee - Samsung
Electronics Co. Ltd.
Electrical Design and
Characterization of Differential Pairs in PBGA Packages
for 10Gb/s Applications
Xingling Zhou and Nancy J. Fang - Agere Systems
Package Electrical
Specifications for Giga Bit Signaling I/Os
Udy Shrivastava, Victor Prokofiev, Chee Hoo Lee,
Anne Augustine, and Lesley Polka - Intel Corporation
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Session
35: Advancements in Wafer Thinning, Bumping and
Interconnect in Support of Wafer Level Packaging
Manufacturing
1:30 p.m. 5:10 p.m.
Committee: Manufacturing Technology
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Session
Co-Chairs:
Tom
Poulin - Aerie Engineering
Tel: +1 909 248 1237
Email: poulintr@cs.com
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Claude
Ladouceur - IBM Canada, Ltd.
Tel: +1 450 534 7314
Fax: +1 450 534 6773
Email: cladouce@ca.ibm.com
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Wafer
Deposition/Metalization and Back Grinding Process
Induced Warpage Simulation
Scott Irving and Yong Liu - Fairchild Semiconductor
Corporation
Cost Performance Wafer Thinning
Technology
Larry Wu, Jacky Chan, C. F Chen, David Tseng, and
C. S Hsiao - Siliconware Precision IIndustry Co.,
Ltd
New Concepts of Material Deposition
Technologies for 300mm Wafer Bumping
Joachim Kloeser and Thomas Oppert - EKRA Eduard
Kraft GmbH
Establishing Control Factors
of Intermetallic Formation within Pb Free Solder
Interconnections at Flip Chip Geometries
Gavin Jackson, Budiman Salam, and Ndy Ekere - University
of Greenwich; Mike Hendriksen - Celestica; Nick
Hoo - ITRI
The Study on the Improvement
of Lead Broken Failure in TCP Using New Sn Pre Plating
Process
Dae Woo Son, Kwan Jai Lee, Jin Hyuk Lee, YeJung
Chung, and - Samsung Electronics Co. Ltd.
Development of Interconnect
Technologies for Embedded Organic Packages
Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi,
and Mitsuharu Shimizu - Shinko Electric Industries
Co., Ltd.
Thermal Simulation and Testing
of Standard and Wide Mold Body Drop In Heat Sink
Plastic Ball Grid Array Packages for Enhanced Heat
Transfer Performance
Bret Zahn - ChipPAC Inc.
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Session
36: Component Technology
1:30 p.m. 5:10 p.m.
Committee: Components & RF
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Session
Co-Chairs:
Leonard
W. Schaper - University of Arkansas
Tel: +1 479 575 8408
Fax: +1 479 575 2719
Email: schaper@uark.edu
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Rao
Bonda - Motorola, Inc.
Tel: +1 480 413 6121
Fax: +1 480 413 4511
Email: rao.bonda@motorola.com3
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Design Rule Development for
Electrical Modeling of RF Multilayer Packaging Inductors
Mekita F. Davis, Rana J. Pratap, Stephane Pinel,
Umesh Jalan, Dung Kunm Kim, Joy Laskar, and Gary
May - Georgia Institute of Technology
A New System on a Chip (SOC) Technology ¡VHigh
Q Post Passivation Inductors
M. S. Lin, Ling Chen, J. Y. Lee, K. H. Wan, H. M.
Chen, Kevin Chou, Roger Hsiao, and Eric Lin - Megic
Corp
Analysis of High Q Inductors
Realised using Wafer Level Packaging techniques
Xiao Sun, Geert Carchon, Walter De Raedt, and Eric
Beyne - IMEC
New Design for High Reliability, Fillet Less Thick
Film Chip Resistors
Yaron Kadim and Leonid Akhtman - Vishay Israel Ltd.
Integration and High Frequency
Characterization of PWB Compatible Pure Barium Titanate
Films Synthesized by Modified Hydrothermal Techniques
(< 100 C)
Devarajan Balaraman, P Markondeya Raj, Swapan Bhattacharya,
Lixi Wan, Madhavan Swaminathan, and Rao R. Tummala
- Georgia Institute of Technology
Development of a PWB with
Resin Capacitor for RF Module Substrate
Yasushi Shimada, Kazuhisa Otsuka, and Yoshitaka
Hirata - Hitachi Chemical Co., Ltd.
Tunable Ferroelectric Capacitor
with Low Loss Electrodes Fabricated using Revverse
Side Exposure
Yong Kyu Yoon Yoon and Mark Allen - Georgia Institute
of Technology
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Sponsors:
 
©2003, ECTC |
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