Title: Low Cost Wafer-Level 3-D Integration without TSV

Most of the wafer level 3-D technologies are using Through-Silicon Vias (TSV). The main barriers for these approaches are high cost, issues with electrical isolation within the Si via, and the need for high capital investments for equipment which is not used in WLP up to now.

A planar integration technology of ultra-thin bare die in a Wafer-Level Thin-Film technology to yield a high-density module will be presented here. This Thin Chip Integration (TCI) technology consists of one or more ultra-thin chips which are stacked on a larger, standard thickness chip, and which are interconnected by a thin film routing. The wafer level thinning of the die to 20 – 40 μm allows redistribution technology to be used for die-to-die integration. The die are bonded using an adhesive on the carrier chip at wafer-level. A standard thin film multilayer is implemented in a planar fashion on top of the embedded system. The metallization is based on a TiW / Cu seed layer, which is subsequently electroplated. Cyclotene 4000 (Photo-BCB) is used as interlevel low k dielectric. The final metallization opens the possibility to stack a FC on top of the embedded chips. The final module consists of an embedded IC on a CMOS or sensor wafer with a third IC FC-bonded on top.

An example of this approach will be presented in details including electrical tests and reliability results. All steps are done at wafer level, therefore enabling a low cost technology which can be manufactured using existing standard redistribution infrastructure. This unique module concept can lead to new applications that would not otherwise be feasible. It will lead the packaging world to new 3-D packages.