Technical Program

Program Sessions: Wednesday May 31st 9:30 AM – 12:35 PM

Session 1: Heterogeneous Chiplet Integration
Committee: Packaging Technologies
Room: Palazzo D

Session Co-Chairs:

Andrew Kim
Apple, Inc.
Email: [email protected]

Mike Gallagher
Dupont Electronics and Imaging
Email: [email protected]

Papers:

1. Ultra High Density Low Temperature SoIC with Sub-0.5 µm Bond Pitch
Han-Jong Chia – Taiwan Semiconductor Manufacturing Company, Ltd.
Shih-Peng Tai – Taiwan Semiconductor Manufacturing Company, Ltd.
Ji James Cui – Taiwan Semiconductor Manufacturing Company, Ltd.
Chuei-Tang Wang – Taiwan Semiconductor Manufacturing Company, Ltd.
Chih-Hang Tung – Taiwan Semiconductor Manufacturing Company, Ltd.
Kuo-Chung Yee – Taiwan Semiconductor Manufacturing Company, Ltd.
Douglas C. H. Yu – Taiwan Semiconductor Manufacturing Company, Ltd.

2. Process Integration of Photonic Interposer for Chiplet-Based 3D Systems
Damien Saint-Patrice – CEA-LETI
Stephane Malhouitre – CEA-LETI
Myriam Assous – CEA-LETI
Thierry Pellerin – CEA-LETI
Remi Velard – CEA-LETI
Leopold Virot – CEA-LETI
Edouard Deschaseaux – CEA-LETI
Maria-Luisa Calvo-Munoz – CEA-LETI
Karim Hassan – CEA-LETI
Stephane Bernabe – CEA-LETI
Yvain Thonnart – CEA-LETI
Jean Charbonnier – CEA-LETI

3. Aggressive Pitch Scaling (sub-0.5 µm) of W2W Hybrid Bonding Through Process Innovations
Tyler Sherwood – Applied Materials, Inc.
Raghav Sreenivasan – Applied Materials, Inc.
Jason Appell – Applied Materials, Inc.
Raghuveer Patlolla – Applied Materials, Inc.
Kun Li – Applied Materials, Inc.
Ki Cheol Ahn – Applied Materials, Inc.
Joe Salfelder – Applied Materials, Inc.
Thomas Kasbauer – EV Group, Inc.
Gernot Probst – EV Group, Inc.
Jurgen Burggraf – EV Group, Inc.
Thomas Uhrmann – EV Group, Inc.
Ryan Ley – Applied Materials, Inc.

4. Design Space Exploration (DSE) for over-136 GB/s IO Bandwidth with LPDDR5X SDRAM Packages on SOC Package in 200 mm³
Heeseok Lee – Samsung Electronics Co., Ltd.
Jun So Pak – Samsung Electronics Co., Ltd.
James Jung – Samsung Electronics Co., Ltd.
Jisoo Hwang – Samsung Electronics Co., Ltd.

5. 3D Stacking of Heterogeneous Chiplets on Modified FOWLP Platform with Thru-Silicon Redistribution Layer
Tai Chong Chai – Institute of Microelectronics A*STAR
Boon Long Lau – Institute of Microelectronics A*STAR
Lim Pei Siang Sharon – Institute of Microelectronics A*STAR
David Ho Soon Wee – Institute of Microelectronics A*STAR
Rob Van Kampen – Qorvo, Inc.
Paul Castillou – Qorvo, Inc.
lance barron – Qorvo, Inc.
Mickael Renault – Qorvo, Inc.
jay ko – Qorvo, Inc.
Jonathan Hammond – Qorvo, Inc.

6. Same Size Mold Chase Technology for Effective Stack Die Architectures
Nabankur Deb – Intel Corporation
Xavier Brun – Intel Corporation
Yoshihiro Tomita – Intel Corporation
Chris Masuyama – Towa Corporation
Naoki Hamada – Towa Corporation
Yoshikazu Hirano – Towa Corporation

7. A Novel Chiplet Integration Architecture Employing Pillar-Suspended Bridge with Polymer Fine-Via Interconnect
Yasuhiro Morikawa – ULVAC, Inc.
Meiten Koh – Taiyo Ink Mfg. Co., Ltd.
Hiroyuki Hashimoto – Tohoku University
Chuantong Chen – Osaka University
Wangyun Li – Osaka University
Ichiro Kono – AOI Electronics
Shinji Wakisaka – Oume Electronics
Ken Ukawa – Sumitomo Bakelite Co., Ltd.
Takafumi Fukushima – Tohoku University
Katsuaki Suganuma – Osaka University
Yoichiro Kurita – Tokyo Institute of Technology