Technical Program
Thursday, May 31, 2012
Session 19: Thru Via Technologies
1:30 PM - 5:10 PM
Committee: Advanced Packaging
Harbor Island II
Session Co-Chairs:
|
Rozalia Beica Lam Research AG T +43 (0) 676 8204 1233 F Rozalia.Beica@lamrc.com |
Sam Karikalan Broadcom Corporation T +1-949-926-7296 F samk@broadcom.com |
Papers:
1. 1:30 PM - Robust TSV Via-Middle and Via-Reveal Process Integration Accomplished through Characterization and Management of Sources of Variation
N. Kumar - Applied Materials, Inc.
S. Ramaswami - Applied Materials, Inc.
J. Dukovic - Applied Materials, Inc.
J. Tseng - Applied Materials, Inc.
R. Ding - Applied Materials, Inc.
N. Rajagopalan - Applied Materials, Inc.
B. Eaton - Applied Materials, Inc.
R. Mishra - Applied Materials, Inc.
R. Yalamanchili - Applied Materials, Inc.
Z. Wang - Applied Materials, Inc.
S. Xia - Applied Materials, Inc.
K. Sapre - Applied Materials, Inc.
2. 1:55 PM - A Novel Scallop Free TSV Etching Method in Magnetic Neutral Loop Discharge Plasma
Yasuhiro Morikawa - Ulvac, Inc.
Takahide Murayama - Ulvac, Inc.
Toshiyuki Sakuishi - Ulvac, Inc.
Manabu Yoshii - Ulvac, Inc.
Koukou Suu - Ulvac, Inc.
3. 2:20 PM - Electrical and Morphological Assessment of Via Middle and Backside Process Technology for 3D Integration
Jean-Philippe Colonna - CEA-LETI
Perceval Coudrain - STMicroelectronics
Gennie Garnier - CEA-LETI
Pascal Chausse - CEA-LETI
Roselyne Segaud - CEA-LETI
Christophe Aumont - STMicroelectronics
Amandine Jouve - CEA-LETI
Nicolas Hotellier - STMicroelectronics
Thomas Frank - STMicroelectronics
Catherine Brunet-Manquat - CEA-LETI
Severine Cheramy - CEA-LETI
Nicolas Sillon - CEA-LETI
4. 3:30 PM - Process Modeling of Dry Etching for the 3D-Integration with Tapered TSVs
Martin Wilke - Fraunhofer IZM
Michael Töpper - Fraunhofer IZM
Hue Quoc Huynh - Fraunhofer IZM
Klaus Dieter Lang - Fraunhofer IZM
5. 3:55 PM - All-Wet Cu-Filled TSV Process using Electroless Co-Alloy Barrier and Cu Seed
Fumihiro Inoue - Kansai University
Tomohiro Shimizu - Kansai University
Hiroshi Miyake - Kansai University
Ryohei Arima - Kansai University
Shoso Shingubara - Kansai University
6. 4:20 PM - Thermal effects on Through-Silicon Via (TSV) Signal Integrity
Manho Lee - KAIST
Jonghyun Cho - KAIST
Joohee Kim - KAIST
Jun So Pak - KAIST
Hyungdong Lee - Hynix Semiconductor, Inc.
Junho Lee - Hynix Semiconductor, Inc.
Kunwoo Park - Hynix Semiconductor, Inc.
Joungho Kim - KAIST
7. 4:45 PM - Enhanced Barrier Seed Metallization for Integration of High-Density High Aspect-Ratio Copper-Filled 3D Through-Silicon Via Interconnects
Yann Civale - IMEC
Silvia Armini - IMEC
Harold Philipsen - IMEC
Augusto Redolfi - IMEC
Dimitrios Velenis - IMEC
Kristof Croes - IMEC
Nancy Heylen - IMEC
Zaid El-Mekki - IMEC
Kevin Vandersmissen - IMEC
Gerald Beyer - IMEC
Bart Swinnen - IMEC
Eric Beyne - IMEC
