2025 IEEE 75th Electronic Components and Technology Conference

Gary Dagastine
co-Media Relations Director
+1 518 785 2724
[email protected]

Chris Burke
co-Media Relations Director
[email protected]

Paper 1.2, Face-Down Bonding and Heterogeneous Chiplet Integration by Using Bumpless Chip-on-Wafer (COW) with Waffle Wafer Technology, Y. Satake et al, Murata - Institute of Science Tokyo - Panasonic Connect Co. Ltd

• Paper 1.2 with caption
• Paper 1.2 Figure

Paper 2.6, All-SMF Arrays for Co-Packaged Optics – Optimizing Cost, Complexity and Performance, N. Mehta et al, NVIDIA

• Paper 2.6 with caption
• Paper 2.6 Figure 4

Paper 4.2, Package Warpage Reduction for Large CoWoS-R Packages, Yu-Hsiang et al, TSMC

• Paper 4.2 with caption
• Paper 4.2 Figure 6a
• Paper 4.2 Figure 6b

Paper 5.6, RF Si Interposer Platform for Chiplet-based Heterogenous Systems, X, Sun et al, IMECn

• Paper 5.6 Figures 2 and 7 with caption
• Paper 5.6 Figures 2 and 7

Paper 9.4, Self-formed Barrier using Cu-Mn Alloy Seed applied to a 400nm Pitch Wafer-to-Wafer Hybrid Bonding Technology, S. Van Huylenbroeck et al, IMEC

• Paper 9.4 with caption
• Paper 9.4 Figure 11

Paper 14.4, Development of A Novel WoWoW Process for 1 and 1.3-inch 50 Megapixel Three-Wafer-Stacked CMOS Image Sensor with DNN Circuits, K. Shimizu et al, Sony

• Paper 14.4 Figure 6 with caption
• Paper 14.4 Figure 6

Paper 18.7, Isothermal Shock Testing on Flip-Chip Interconnects, M. Häusler et al, TU Dresden

• Paper 18.7 Figures 1 and 8 with caption
• Paper 18.7 Figure 1
• Paper 18.7 Figure 8

Paper 22.1, Hybrid Bonding with Fluidic Self Alignment - Process Optimization and Electrical Test Vehicle Fabrication, F. Eid et al, Intel

• Paper 22.1 Figure 1 with caption
• Paper 22.1 Figure 1

Paper 24.5, Predictive Modelling of Thin Films Properties Using An Experimental and Simulation-Based Approach, D.K. Lim et al, Nat’l Univ. of Singapore and Micron Technology

• Paper 24.5 Figure 5 with caption
• Paper 24.5 Figure 5

Paper 28.4, The Influence of Full IMC Structure on Micro-Bump Electromigration Performance, Chung-Yu Chiu et al, TSMC

• Paper 28.4 Figure 6 with caption
• Paper 28.4 Figure 6

Paper 29.6, Design and Fabrication of Bendable Double-layer RDL Metallization Based on FOWLP for In-Mold Flexible Hybrid Electronics (iFHE), C. Liu et al, Tohoku Univ

• Paper 29.6 Figure with caption
• Paper 29.6 Figure

Paper 31.5, Localized Formation of Laser Non-Conductive Film (NCF) on 10 µm Diameter Bumps, Applied to 20 µm Pitch Chiplet Chip-on-Wafer (CoW) Bonding, J. Shin et al, ETRI - Hanbat National Uni

• Paper 31.5 Figure 10 with caption
• Paper 31.5 Figure 10

Paper 32.3, Ultra-Fast Cu Polymer Hybrid Bonding with Electroless Passivation Layer for Cost-Effective High IO Interconnection Stacking, Yu-Lun Liu et al, National Yang Ming Chiao Tung Univ. and Tokyo Ohka Kogyo Co. LTD

• Paper 32.3 Figure 8 with caption
• Paper 32.3 Figure 8

IP session 37, Fast And Accurate Machine Learning Prediction of Back-End-Of-Line Thermal Resistances in Backside Power Delivery and Chiplet Architectures, P. Chowdhury et al, IBM

• IP session 37 Figures 1 and 3 with caption
• IP Session 37 Figures 1 and 3.png

IP session 38, Signal and Power Integrity Optimization Using Novel Bridge Die and Copper Post Interconnect Design in 2.xD Packaging for Wide IO Applications, Y. Na et al, HANA Micron Inc. - Myongji University - Swevenz Inc

• IP Session 38 Figures 1 and 7 with caption
• IP Session 38 Figure 1
• IP Session 38 Figure 7

IP session 39, Advanced Face-To-Back CoW 2.0-µm pitch Cu–Cu Hybrid Bonding Process for Three Layer-Stacked 3D Heterogeneous Integration, A. Urata et al, Sony

• IP Session 39 Figures 1, 5 and 13 with caption
• IP Session 39 Figure 1
• IP Session 39 Figure 5
• IP Session 39 Figure 13

IP session 40, Experimental Demonstration of High-Power Thermal Test Vehicle using Two-Phase Cooling for AI Datacenters, 5G RAN, and Edge Compute Nodes, Yang Liu et al, Nokia Bell Labs

• IP Session 40 Figures 1 and 5 with caption
• IP Session 40 Figures 1 and 5

IP session 41, Hybrid Voltage Regulators for High Performance Computing - Analytical Models and Design Methodology, S. Abdelzaher et al, University of Illinois

• IP Session 41 Figure 5a and 5b with caption
• IP Session 41 Figure 5a
• IP Session 41 Figure 5b