Technical Program
Thursday, June 02, 2022
Session 19: Advances in Fan-Out Panel Level Packaging
1:30 PM - 5:10 PM
Committee: Packaging Technologies
Room: Silver Pearl 1
Session Co-Chairs:
|
Albert Lan Applied Materials Albert_Lan@amat.com |
Jie Fu Apple Inc. fujie6@gmail.com |
Papers:
1. Panel Level Packaging – Where are the Technology Limits?
Tanja Braun - Fraunhofer IZM
Ole Hölck - Fraunhofer IZM
Mattis Obst - Fraunhofer IZM
Steve Voges - Fraunhofer IZM
Ruben Kahle - Fraunhofer IZM
Lars Böttcher - Fraunhofer IZM
Mathilde Billaud - Fraunhofer IZM
Lutz Stobbe - Fraunhofer IZM
Karl-Friedrich Becker - Fraunhofer IZM
Rolf Aschenbrenner - Fraunhofer IZM
Marcus Voitel - TU Berlin
2. Study of Reliable Via Structure for Fan Out Panel Level Package (FOPLP)
Da-Hee Kim - Samsung Electronics Co., Ltd
Jae-Ean Lee - Samsung Electronics Co., Ltd
Gyujin Choi - Samsung Electronics Co., Ltd
Sunguk Lee - Samsung Electronics Co., Ltd
Giho Jeong - Samsung Electronics Co., Ltd
Hongwon Kim - Samsung Electronics Co., Ltd
Seokwon Lee - Samsung Electronics Co., Ltd
Dong wook Kim - Samsung Electronics Co., Ltd
3. A Hybrid Panel Level Package (Hybrid PLP) Technology Based on a 650-mm x 650-mm Platform
Eoin O´Toole - Amkor Technology
Luís Silva - Amkor Technology
Filipe Cardoso - Amkor Technology
José Silva - Amkor Technology
Aníbal Coelho - Amkor Technology
Márcio Souto - Amkor Technology
Nuno Delduque - Amkor Technology
José Silva - Amkor Technology
WonChul Do - Amkor Technology
JinYoung Khim - Amkor Technology
4. Package Reliability Evaluation of 600mm FOPLP with 6-Sided Die Protection with 0.35mm Ball Pitch
Jacinta Aman Lim - nepes Corporation
Brett Dunlap - nepes Corporation
Sungeun Hong - nepes Corporation
Hyung-Jin Shin - nepes Corporation
Byung Cheol Kim - nepes Corporation
5. Panel-Based Large-Scale RDL Interposer Fabricated Using 2-Micron Pitch Semi-Additive Process for Chiplet-Based Integration
Hiroshi Kudo - Dai Nippon Printing (DNP) Co., Ltd.
Takamasa Takano - Dai Nippon Printing (DNP) Co., Ltd.
Hiroshi Mawatari - Dai Nippon Printing (DNP) Co., Ltd.
Daisuke Kitayama - Dai Nippon Printing (DNP) Co., Ltd.
Takahiro Tai - Dai Nippon Printing (DNP) Co., Ltd.
Tsuyoshi Tsunoda - Dai Nippon Printing (DNP) Co., Ltd.
Satoru Kuramochi - Dai Nippon Printing (DNP) Co., Ltd.
6. Harnessing the Power of 4nm Silicon with Gen 2 M-Series™ Fan-OUT and Adaptive Patterning® Providing Ultra-High-Density 20µm Device Bond Pad Pitch
Robin Davis - Deca Technologies
Benedict San Jose - Deca Technologies
7. All Copper Is Not Created Equal — Examples of Grain Engineering In Plating
Yun Zhang - Shinhao Materials LLC
Jing Wang - Shinhao Materials LLC
Peipei Dong - Shinhao Materials LLC
Xingxing Zhang - Shinhao Materials LLC
Wei Zhao - Shinhao Materials LLC
Josh Liang - Shinhao Materials LLC
Michael Herkommer - Umicore Galvanotechnik GmbH
Klaus Leyendecker - Umicore Galvanotechnik GmbH
Volker Wohlfarth - Umicore Galvanotechnik GmbH
