1. Direct Die-to-Wafer Hybrid Bonding Using Plasma Diced Dies and Bond Pad Pitch Scaling Down to 2 µm
Ye Lin — imec
Pieter Bex — imec
Koen Kennes — imec
Jaber Derakhshandeh — imec
Prathamesh Dhakras — imec
Samuel Suhard — imec
Carine Gerets — imec
Sven Dewilde — imec
Violeta Georgieva — imec
Anne Jourdain — imec
Gerald Beyer — imec
Eric Beyne — imec
2. Multi-Functional Self-Assembled Monolayer (SAM) for Chip-to-Chip and Chip-to-Wafer Hybrid Bonding Yield Enhancement
Murugesan Mariappan — Tohoku University
K Mori — T-Micro
H Hashimoto — Tohoku University
A Kurachi — JX Metals Corporation
T Imori — JX Metals Corporation
T Fukushima — Tohoku University
3. 3D Heterogeneous Integration With Sub-3µm Bond Pitch Chip-to-Wafer Hybrid Bonding
Yi Shi — Intel Corporation
Haris Niazi — Intel Corporation
Michael Baker — Intel Corporation
Yuan Meng — Intel Corporation
Ashish Dhall — Intel Corporation
Xavier Brun — Intel Corporation
4. Novel Three-Layer Stacking Process With Face-To-Back CoW 6 µm-Pitch Hybrid Bonding
Akihiro Urata — Sony Semiconductor Solutions Corporation
Takahiro Kamei — Sony Semiconductor Solutions Corporation
Akihisa Sakamoto — Sony Semiconductor Solutions Corporation
Hirotaka Yoshioka — Sony Semiconductor Solutions Corporation
Kan Shimizu — Sony Semiconductor Solutions Corporation
Yoshihisa Kagawa — Sony Semiconductor Solutions Corporation
Hayato Iwamoto — Sony Semiconductor Solutions Corporation
5. Dielectric Stack Optimization for Die-level Warpage Reduction for Chip-to-Wafer Hybrid Bonding
Chandra Rao Bhesetti — Institute of Microelectronics A*STAR
Dileep Kumar Mishra — Institute of Microelectronics A*STAR
Nagendra Sekhar Vasarla — Institute of Microelectronics A*STAR
Sasi Kumar Tippabhotla — Institute of Microelectronics A*STAR
Ismael Cereno Daniel — Institute of Microelectronics A*STAR
Ser Choong Chong — Institute of Microelectronics A*STAR
King Jien Chui — Institute of Microelectronics A*STAR
Srinivasa Rao Vempati — Institute of Microelectronics A*STAR
6. Low Temperature Wafer Level Hybrid Bonding Enabled by Advanced SiCN and Surface Activation
Fumihiro Inoue — Yokohama National University
Atsushi Nagata — Tokyo Electron Kyushu, Ltd.
Junya Fuse — Yokohama National University
Sodai Ebiko — Yokohama National University
Ryosuke Sato — Yokohama National University
Kenichi Saito — Tokyo Electron, Ltd.
Yoshihiro Kondo — Tokyo Electron Kyushu, Ltd.
Takuo Kawauchi — Tokyo Electron, Ltd.
Junghwan Park — SK Hynix, Inc.
Chiwoo Ahn — SK Hynix, Inc.
Myeonghyeon Kim — SK Hynix, Inc.
Jiho Kang — SK Hynix, Inc.
7. A Study on D2W Hybrid Cu Bonding Technology for HBM Multi-Die Stacking
Hyeonmin Lee — Samsung Electronics Co., Ltd.
Jihoon Kim — Samsung Electronics Co., Ltd.
Hyungchul Shin — Samsung Electronics Co., Ltd.
Wonil Lee — Samsung Electronics Co., Ltd.
Aeni Jang — Samsung Electronics Co., Ltd.
Hyuekjae Lee — Samsung Electronics Co., Ltd.
Byungchan Kim — Samsung Electronics Co., Ltd.
Ilhwan Kim — Samsung Electronics Co., Ltd.
Dongjoon Oh — Samsung Electronics Co., Ltd.
Jumyong Park — Samsung Electronics Co., Ltd.
Un-Byoung Kang — Samsung Electronics Co., Ltd.
Dae-Woo Kim — Samsung Electronics Co., Ltd.
