Technical Program

Session 24: Fan-Out Wafer Level Packaging Developments and Applications
Committee: Assembly & Manufacturing Technology

Session Co-Chairs:

Jan Vardaman
Techsearch International
T
jan@techsearchinc.com
Paul Tiner
Texas Instruments
T +1-469-471-3565
p-tiner@ti.com

Papers:

1. Multi-Tier N=4 Binary Stacking, Combining Face-to-Face and Back-to-Back Hybrid Wafer-to-Wafer Bonding Technology
Stefaan Van Huylenbroeck - IMEC
Joeri De Vos - IMEC
Lieve Teugels - IMEC
Serena Iacovo - IMEC
Ferenc Fodor - IMEC
Andy Miller - IMEC
Geert Van der Plas - IMEC
Gerald Beyer - IMEC
Eric Beyne - IMEC

2. 600mm FOPLP as a Scale Up Alternative to 300mm FOWLP With 6-Sided Die Protection
Jacinta Aman Lim - nepes Corporation
Yun-Mook Park - nepes Corporation
Edil De Vera - nepes Corporation
Byung-Cheol Kim - nepes Corporation
Brett Dunlap - nepes Corporation

3. Demonstration of Fine Pitch RDL in Fan-Out Panel Level Packaging
Dowan Kim - Samsung Electronics Company, Ltd.
Seokbong Park - Samsung Electronics Company, Ltd.
Mina Heo - Samsung Electronics Company, Ltd.
Daeyeon Choi - Samsung Electronics Company, Ltd.

4. A Novel Multi-chip Stacking Technology Development Using a Flip-Chip Embedded Interposer Carrier Integrated in Fan-Out Wafer-Level Packaging
Yu-Min Lin - Industrial Technology Research Institute
Wei-Lan Chiu - Industrial Technology Research Institute
Chao-Jung Chen - Industrial Technology Research Institute
Hsiang-En Ding - Industrial Technology Research Institute
Ou-Hsiang Lee - Industrial Technology Research Institute
Ang-Ying Lin - Industrial Technology Research Institute
Ren-Shin Cheng - Industrial Technology Research Institute
Sheng-Tsai Wu - Industrial Technology Research Institute
Tao-Chih Chang - Industrial Technology Research Institute
Hsiang-Hung Chang - Industrial Technology Research Institute
Wei-Chung Lo - Industrial Technology Research Institute

5. Comprehensive Study of Thermal Impact on Warpage Behaviour of FOWLP with Different Die to Mold Ratio
Ser Choong Chong - Institute of Microelectronics
Siak Boon Lim - Institute of Microelectronics
Wen Wei Seit - Institute of Microelectronics
Tai Chong Chai - Institute of Microelectronics
Debbie Claire Sanchez - ERS electronic GmbH

6. A Novel Chip Placement Technology for Fan-Out WLP using Self-Assembly Technique with Porous Chuck Table
Tadatomo Yamada - LINTEC Corporation
Ken Takano - LINTEC Corportaion
Toshiaki Menjo - LINTEC Corporation
Shinya Takyu - LINTEC Corporation

7. Extremely Large Exposure Field with Fine Resolution Lithography Technology to Enable Next Generation Panel Level Advanced Packaging
John Chang - Onto Innovation
Timothy Chang - Onto Innovation
Casey Donaher - Onto Innovation
Perry Banks - Onto Innovation
Keith Best - Onto Innovation
Aries Peng - Onto Innovation